I've worked with Allegro HDL since way before it was called that. I'm new to OrCAD / CIS. I've been told to use Allegro Design Entry CIS, but everything including tutorials are referencing Design Capture. What is the difference? I've searhed for a comparison or description of differences and can't find anything. Will the tutorials also apply to Design Entry? I've been told that even though we are using CIS we aren't actually implementing the CIS database side of things.
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Difference between Allegro Design Entry and Allegro Design Capture
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How to make a slot into a PCB
Hi,
designing a daughter board in which a slot is needed to make an slot to save large components on the main board.
The daughter board has a dimensions of 5x5mm and the daughter board need a slot of 1x1mm.
Starting the design, I placed the board outline, route keepin... and for not having troubles in future routing, I would like to add the hole now.
How can I draw/place this slot?
- Do I need to draw a board outline shape inside the current shape?
- Do I need to create a new layer with different parameters?
- Would it be better to define a new padstack with slot dimensions, and then a mechanical symbol with this padstack?
If there is another better way to perform this action, it would be welcome.
KR!
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Multiple schematic pages in design
What is the purpose of having multiple schematic pages in a design? The only thing I can think of is if the design has multiple circuit boards, i.e. a daughter board.
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4 Layer PCB, Inner planes VCC and GND what to do with outer layers?
So I have designed a 4 layer PCB with internal GROUND and VCC plane. Should I create a plan for the outer 2 layers and if so should I make those ground planes as well?
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How to change color component(s) with SKILL ?
Duplicated with PCB Skill , please ignore it.
Thanks ,
Hung
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Differential pair constraint region problem
Hello,
I have a problem with routing the differential pair out of the constraint region (under a big BGA package). Single ended tracks change the width on the border of the constraint region and this works fine. The problem is with the differential pairs as they don't resize directly on the constraint region border but they resize in random place (the point where I click the mouse) later.
Here I have some screens:
1) This presents that single-ended track resizing works OK. On the constraint region border the track resizes correctly.
2) Here is the actual problem. When I am in the routing mode (F3) and when I move the diff-pair out of the constraint region it doesn't resize automatically.
and then I click the left mouse button outside of the constraint region and the diff-pair is resized directly in that point:
The license I am using is "Allegro PCB Designer (was Performance L)". The Allegro version is 16.6 S050 (v16-6-112DX).
Do I have to configure anything else to get it working?
Best regards and thank you in advance for your help,
Krzysztof
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Windows 10 - anyone, anyone?
Just curious if anyone has tried Allegro/Capture on Win 10 yet and what their experience was? How about min recommendations for a new laptop? I am really wanting to get onboard with W10 but fear that I will be navigating this alone for a while... Feedback appreciated.
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Non-Vectorized text for Allegro
Hi All,
Is there a font that represents the text exactly or very close to the fonts used in Allegro?
Some fonts look very close, but it does look little off from what I can tell just by comparing the PDF and the board data.
Please advise if anyone has had luck duplicating the board data.
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Foot print Creation in allegro -Cadence
Hi all,
I have a doubt regarding the foot print creation in allegro- Cadence.I want to make a processor and corresponding discrete as a single foot print with Refdes of individual's .
Is it possible????
For example I am instantly using power section Converter IC and discrete for all my layout. But each time I have to work on these things separately.
Eagerly waiting for the response.........
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Is it possible to create a variant schematic with different footprints from the base schematic?
Hi,
Is it possible to create a variant schematic using a different footprint from the base schematic in Design Entry HDL? Example, my base schematic uses surface mount components, I would like to create variant schematic using through hole components instead. Is this possible? How?
Thanks,
Maberu
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Re-Display reference designator
If deleted for any reason, reference designator (for example on ASSY_TOP and/or SILK_TOP) can reapear if component is unplaced and placed again.
Is there another way to display again deleted reference designator without unplace-place operation?
Thanks.
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Export and Import between Cadence Allegro 16.5 and OrCAD Layout Plus 16.2.0
Hi.
Does anyone have experience of exporting/importing designs between Cadence Allegro 16.5 and OrCAD Layout Plus 16.2.0.
What is the best method to use?
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W- (SPMHA1-230): Database has a non-recoverable corruption. Contact Cadence customer support. E- Cannot load symbol 'SW_3PIN_SPDT'
Good afternoon
Currently I work with a PCB and I need to modify a switch. I made the switch in .dra but when I want to put on the .brd file, this message appears
W- (SPMHA1-230): Database has a non-recoverable corruption. Contact Cadence customer support.
E- Cannot load symbol 'SW_3PIN_SPDT'
I changed some parts on the design but always is the same.
I don't understand what happen, Can you help me please?
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Orcad App getting on PCB editor Menu
Hi Friends
I installed few Orcad apps from Orcad capture market place. But not getting hint how to make it to reflect on PCB editor Menu.
I knew to set skill file (.il) . But this is an .exe file. After installing I restarted tool but not reflecting in editor menu
(App detail CaptureDesignCompare_1.0 ,CaptureDesignCompare_1.0,CaptureDesignCompare_1.0,PadEscClineWidth_1.0.exe)
Thanks
GK
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Cannot find trace tapering option in Route->Gloss
Hi all,
I want to do trace tapering.
I googled and found I need to Route->Gloss->Fillet and Tapered Tarce.
But I don't even have this option. I know this is a function added to OrCAD PCB Editor 16.5. And I am using 16.5.
Is there any parameter I need to set to activate this menu? Or at least is there a work-around?
Thank you!
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How can I plot Pin-Pout in pspice ?
I want to plot gm-Ids, Pgain-Pout, IIP3-Id etc. graphics in pspice. But in DC sweep analysis, you can define just current or voltage. How can I define Pin or Pout or Cgs ?
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Orcad capture symbol copy
I have to symbol editors open in schematic capture and I want to copy one symbol into the other. When a do a copy and past the pins cumber do not copy. Is there a way I can preserve the pin numbers on a symbol copy and past?
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variant editor won't see my DNI components
Hi,
I am trying to use Variant Editor to make a DNI BOM report, as per our organization's process. I open Variant Editor, do a New Variant, fill in the four fields, click OK. My new variant appears in the left pane, with sub-folders of Components and Functions.
The problem is that the Components folder is empty - it does not populate with my DNI components as I expect it to.
I have an older project which works fine doing the same thing. I've checked every setting and dialog that I can think of that might possibly be related, but I can't find a difference. The newer project just doesn't work. I opened the various dialogs side-by-side, looking for a setting that is different, but found nothing different except the name.
Another hint: When I run Packager / Bill of Materials, select Variant BOM, and view the output, at the end of the file is "DNI Component List:", but the list is empty. On the older project, my DNI parts show up in the file as expected.
What could be set incorrectly in the project?
I'm running 16.6-S013 (v16-6-112AL), dated 7/1/2013 .
Thanks for any advice,
Pete
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Asymetric thermal relief connections problems with irregular pad
Hello Cadence Community!
I have problem with thermal relief connections.
I made padstack for goldpin connector, which has on bottom layer oblong shape and circular shape on other layers. Drill and circular shape has -0.5mm offset in Y direction.
On bottom layer thermal relief is correct:
But on other layers thermal relief is asymetric:
Is there any method to make this thermal relief symetric?
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Constraint Manager Doubt - Net Properties
Hello,
working in new design I need to update the netlist from capture. After updating, at CM on PCB Editor some signals are shown with a pink arrow on their left (
).
What does this arrow means?
KR!
* EDIT: Checking schematic, I have no selected any signal (which could return this behaviour).
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