Hi,
Please help on the generation of BOM. While generating bom, parts are placed per row.
Example:
Row 1 - C1 , C0805C104K3RACTU
Row 2 - C2, C0805C104K3RACTU
How can I make it this way:
Row 1 - C1, C2 - C0805C104K3RACTU
Thanks,
Maberu
Hi,
Please help on the generation of BOM. While generating bom, parts are placed per row.
Example:
Row 1 - C1 , C0805C104K3RACTU
Row 2 - C2, C0805C104K3RACTU
How can I make it this way:
Row 1 - C1, C2 - C0805C104K3RACTU
Thanks,
Maberu
I have 3 ground planes. Say AGND, DGND and PGND. They are meant to be separated entirely, except to only join in them at a single point at where I wanted. However, if I connect them together in the schematic, the rats nets show them to be a single net and any via would connect them unwantedly. How do I distinguish them? I tried separating them in the schematic level, connect each grounds separately in the layout. Once these are done, I connect them together in the schematic and hope I can connect them in PCB Editor, but everything messes up. Does anyone know how to solve this?
Thank you.
Hi All
I want to get the properties that are on the nets in a Orcad schematic out into a file, but without having to export lots that I am not interested in, i.e. not using the Export properties. This is due to not being able to use the Allegro flow due to the way the circuit has been created.
Any help here would be greatly appreciated.
Hi,
When creating a part I add the place bound, I suspect most people do that. In order to see them during the design, I also have to add the Place Bounds in the Artwork film set up, so that I see them in the Views tool. So far so good.
But when creating the gerbers, those place bounds are there, shorting nets. So I manually have to go remove them from the Artwork film set up... And if I need to do some modifications to the design, I have to go back and add them again.
One way to solve this would be to display the place bounds only when looking at the top (or bottom) layers. But then I would have to do it every time.
This is counterproductive. There must be a better way. What is it??
Anyone here using the "Library Expert" version of this tool? We are considering buying it. It looks like it would save time by creating the footprints automatically after inputting the dimensional data into the tool.
Hello,
Does PCB Designer have the ability to calculate/estimate inductance of a trace / traces?
I am trying to implement a capacitor decoupling network for an IC. I can choose the capacitor value, but the inductance is determined by the PCB trace, via structure, stackup thickness, etc. If PCB Designer can estimate the inductance of the traces between IC and capacitor, then I can calculate the resonance frequency, and make it the same as the clock frequency.
Thanks,
I am currently working with allegro 16.0 licensed version in my office. I can't add sub classes to the art work and also i can't manually place the component to y board any one can help me on this issue
I am adding a image that is the window that i am getting when i try to create artwork...............
When I prepare a project in OrCad Capture, then create netlist for the PCB Editor, after choosing the option to open the board file in allegro PCB Editor , it just displays the message that the project will be saved prior to netlisting . I chose ok then nothing happens . No files are generated and PCB Editor does not open.
Can someone Help Me with this issue?
I am running OrCAD 16.6 Lite
The PCB is cluttered with irrelevant details. I can not see how to reduce them to part references pads and outlines?
Just an overview, I have some though-hole pins on the bottom layer that are high-voltage. On the top surface is a huge polygon or plane designated as GND. On this GND plane, within the vicinity of the high-voltage holes, I wanted to specify a clearance of let's just say 100mils (to avoid arcing from the high-voltage pin to the GND plane).
At present, I manually added to the high-voltage pins some isolation/cavities on the polygon/shape assigned as the GND. This works for now because I have few pins. But when the number of high-voltage pins (and traces or other components) increases, manually defining the isolated areas become impractical.
So my question is, how can we do this automatically at Orcad PCB Editor (v16.6)?
With Altium Designer, I can simply add rules and create SQL-like statements to define that high-voltage pins should always have a 100-mil clearance from any other pin (trace, polygon, and etc).
On a separate question (but somehow related), on the Xsection (for Orcad PCB Editor), when I specify the layer type to be "Plane", I don't seem to see any difference on the actual layer when compared to the layer type being set as "Conductor". On Altium Designer, if a layer is specified as a plane, a polygon covering the entire layer is automatically defined which you can set to any "net" (for example GND). On Orcad PCB, when I set the layer to a "plane", I don't see anything unique happening on the layer. I can still add any shape to this layer like it's a "conductor" type of layer. I may be overlooking something here.
When I am working on the globally assigned (i.e., GND and Supplies) related things like, moving/adding via, slides the Cline, the tool hangs for more than a minute, this happens when I disables the OpenGL properties also???
Anyone can tell, what could be the reason behind this?
Thanks,
Thangapandi Arumugam
Hello everyone,
I am Anirudh THABJUL working as PCB designer in second-Bridge, Paris.
I am designing a schematic for my project in ORCAD CAPTURE CIS. while creating the NETLIST, I got following error
#1 WARNING(ORCAP-36042): Pin "GND" is renamed to "GND#14" as visible power pin of same name already exists in Package ATXMEGAxxxA3UG , U12A: 05- RANGING, RANGING (215.90, 63.50).
How to solve this warning?
Does it effects my routing on PCB layout?
Regards,
Anirudh THABJUL
How to import component file (.cmp)? İ will simulation my board and i need a component file. how can i create .cmp file?
Thanks
Hello Everyone,
I am electronic engineer working in Paris.
I am using ORCAD 16.6 for designing our schematics and PCB layout.
In order to design the PCB layout we need to create NETLIST file right.
So, while creating this netlist i have got following error
" ERROR: File "SNB_PSB.brd" is being edited by user "THABJUL" on date "Mon Nov 30 15:20:05 2015" on system "ANIRUDH_THABJUL". Resolve lock file and re-run netrev.
#1 ERROR(SPMHNI-175): Netrev error detected."
Can any body help me in solving this issue?
Regards,
Anirudh
Hi, when I use our Orcad PCB designer license I see the new style menus but when I switch to Allegro PCB Designer (was Performance L) I get the old style menus. In Orcad PCB Designer I can revert to the old style but in Allegro PCB Designer there seems to be no way to change to the new syle.
Anyone know how to get the new menus to show up ?
Thanks,
Jim O'Mahony
Hi all,
Is there a way to assign color to diff pairs in the 16.6 free viewer?
I tried going to assign color and selecting diff pair on "Find by Name" section and clicked more and selected diff pairs shown and clicking apply then I get an error "E- Command not found: _xdbgrouptype diff_pair "
I was able to get this to work on licensed software so I'm guessing it's just not available in the viewer.
Has anyone had any luck with this? There are people using viewer that like to locate diff pairs easily on the board. (Constraints slightly vary depending on the designer so I'm thinking assigning color by constraints/property might be hard for someone who doesn't use Allegro on regular basis to identify as easy)
Please let me know if anyone has suggestions that may be simple for novice user to use.
Good day!
Anyone here knows any method on checking of acute angles pattern created on smd pin break-out points.
Please refer to the below image. Please help. Thank you.
Hi there!
Recently we made a stupid mistake as following picture: the net "VCC12IN" should connect toJ6E's pinE1 but it's actually "float". The entire J6E was dislocated by one pin space(you could see pin.E25 is empty) . However, the "VCC12IN" I marked with circle is actually not a truely isolated net because it's correctly connetced to J6D's pin.D1. That's why DRC function "check single node nets" is useless here.
Could orcad DRC find this kind of faults in schematic?
Thanks a lot!
Hi there!
There is Fix function in allegro PCB layout to prevent unintentional movement of components. Is there similar function in ORCAD when drawing schematics?
Thanks a lot!
I'm new to PCB and doing my first Project in Orcad 16.6 lite.
I have a circuit with 3 Leds in row and a connector.
I created the pads in paddesigner. Soldermask and pastemask i made the same size.
I created my board and tried to generate gerber files. (rs274x)
Since I have only one layer, I created the top.art and I added the silkscreen top file. Board outline I added manually, because it isn't listed in the Color Dialog box under manufacturing. This also worked.
My problem now: How do I get the solder mask top gerber file ? Isn't it defined by my pads that i made? When I add the solder mask manually nothing happens. Undefind line width is 0.2 mm
What am I missing? Thanks for any help.
Thomas