Is there an easy way to update a symbol with one with a different name ?
↧
Update symbol to desing with different symbol name.
↧
Edit padstack to new name in symbol editor does not change padstack.
If I edit a pins padstack by using modify padstack and selecting the pin , I can edit and save the padstack to the disk and the design but the name of the padstack on the pin does not change. Is this a bug ?
↧
↧
move groups
I have a section of the board all routed, and I'd like to drag that over some, bringing all the routing between the components along. It seems like I need to disconnect traces going to the section, then do a move.
Its seems like 'ripup etch' is the best mode to use.
Is there a better way?
↧
MySQL Community Server Installed on Linux doesn't work with OrCAD CIS, but it works with Windows based MySQL Community Server
Hi,
We are migrating from our Windows based MySQL Community server version 5.0 to Linux based MySQL Community server 5.6 and we are having trouble for this.
This is only happening if we point the MySQL ODBC Driver from computer to Linux Based MySQL Server with below error:
=================================================================================================
ERROR #8012 Database Operation Failed
Please Check Session For More Details
ODBC Error Code: -1
Description: You have an error in your SQL syntax; check the manual that corresponds to your MySQL server version for the right syntax
==================================================================================================
But, if I point the MySQL ODBC Driver from computer to Windows Based MySQL Server, every thing looks fine. The same thing is happening for all the OrCAD CIS users in my comany.
Any software needed to be installed after installing MySQL Community Server on Linux.
Please help us.
↧
Same net spacing (metal to metal)?
Does the "Metal to Metal" spacing constraint apply to same nets? If so, I can't seem to get it to work.
Is it possible to get Allegro to report a DRC for minimum air gaps even if it's the same net?
↧
↧
Problems creating a mirror image of a documentation frame around a PCB.
Hi all,
I have a problem with mirroring and Lines.
I have documentation frame (text + lines) around my board composed of Text and Lines. I am trying to make a mirror image of the frame so I can document the bottom layer (which is already in mirror image ref des, text on PCB, etc).
I have successfully mirrored the text as a page (text that was on the RHS of the page is now on the LHS of the page), but I am completely failing when it comes to the Lines. I can get each individual line to mirror separately, but cannot get the Lines to mirror as a group.
How can I either a) mirror the Lines as an entire page, or b) mirror both the Text and Lines as one page in one go.
The mirror option is available for CLines, but not Lines...
Using 16.6.
Robert.
↧
Unable to create netlist
Hi,
A warning(part name "****"is renamed to "****") is always shown when i try to creat the netlist of my project. So i can't create the netlist of my project. I fixed that problem using setup tab in create netlist. But still i'm not able to generate netlist. No error or warning is shown on the session log. Please have a look at my session log.
Spawning... "E:\Cadence\SPB_16.6\tools\capture\pstswp.exe" -pst -d "E:\APLITE\SCHEMATIC APPLITE\SCHEMATIC APPLITE\APPLITE.DSN" -n "E:\APLITE\SCHEMATIC APPLITE\PCB" -c "E:\Cadence\SPB_16.6\tools/capture/allegro.cfg" -v 3 -l 31 -s "ORCAP-36006;ORCAP-36038;ORCAP-36042" -j "PCB Footprint" -hpath "HPathForCollision"
INFO(ORCAP-36080): Scanning netlist files ...
Loading... E:\APLITE\SCHEMATIC APPLITE\PCB/pstchip.dat
Loading... E:\APLITE\SCHEMATIC APPLITE\PCB/pstchip.dat
Loading... E:\APLITE\SCHEMATIC APPLITE\PCB/pstxprt.dat
Loading... E:\APLITE\SCHEMATIC APPLITE\PCB/pstxnet.dat
packaging the design view...
Exiting... "E:\Cadence\SPB_16.6\tools\capture\pstswp.exe" -pst -d "E:\APLITE\SCHEMATIC APPLITE\SCHEMATIC APPLITE\APPLITE.DSN" -n "E:\APLITE\SCHEMATIC APPLITE\PCB" -c "E:\Cadence\SPB_16.6\tools/capture/allegro.cfg" -v 3 -l 31 -s "ORCAP-36006;ORCAP-36038;ORCAP-36042" -j "PCB Footprint" -hpath "HPathForCollision"
INFO(ORCAP-32005): *** Done ***
How can i fix this issue?
↧
Backdrilling and correct Allegro property use
Looking to make sure that this approach is the correct one or if there is another? Say you have a board with two press fit connectors on the same side, the board is .125 think with 10 layers. You route high speed signals from one connector to another say on layer 4. The press fit connectors have max pin lengths of .035 for one connector and .055 for the other. You set up your backdrilling passes and due to pin length only backdrills the connector with the .035 pin length with the .055 being too long. What is the correct process to get this other connector to backdrilled to the closest layer that will accommodate the .055 pin length ?
↧
Diff pair gap report
My PCB file is not responding, while genarating Diff pair gap report from Allegro-Tools-Qick report. But other PCB files are opening immediately.How to get my Diff pair gap report?
Regards,
Mani
↧
↧
Manual Void Troubles
Hi,
I have a through hole DC/DC buck converter. It is in the middle of a circular board. It is being powered by a plane that is tied to a battery voltage. I am trying to put a circular void around the battery power pin, so that I can pass the battery voltage through an input bypass cap and know that the voltage going into the input pin is being filtered/smoothed. I think I placed a circle void, but there is no void around the pin, which seems to me means there is no void. I still see the circle, but no void. How do you place a circular void around a through hole pin that has the same net name as a plane?
Thanks.
Shaune
↧
Use multiple databases (.DBC) at the same time
Hi,
There is another portion of my company that uses a database. If I already use a database that is a different format is it possible to point to multiple .DBC files at the same time? Or is the only option to toggle between or combine them?
Thanks!
↧
creation of symbols having many pins
Hi,
I'm preparing schematic for my project whose main part is a controller having 136 pins. I drew it as a single package but it looks too complex. It would be better if i could split it into different sections(like power supply,UART part,ADC section). Please explain how can i add the same footprint to those different sections.
↧
Orcad Layout library file .llb from version 16.2 (Layout database 9.2.3) to version 9.2 (Layout Database 9.20)
Hello All,
I have a .llb file saved with orcad layout version 16.2 (layout database 9.2.3) and I need to use it with orcad layout version 9.2 (layout database 9.20). I can add the .llb file saved with 16.2 version to library manager version 9.2, I can see the library in the library list, but I cannot open the footprints. The message is "Failed to load footprint". Is there anybody that can help me?
Thank you very much!!
BR,
Pietro
↧
↧
Illegal character "White space" found in Refdes
Hi,
I'm preparing the schematic for my project. Two errors have been shown hen i tried to create the netlist. It says "Illegal character "White space" found in Refdes of xxxxxxxxx "(ORCAP-36112). Three crystal oscillators are used in my project. Those errors are associated with two of the mentioned crystals named X1 and X2. The other crystal seems fine. All the footprints are designed by me. But i don't know whats wrong the those two components. Any help would be appreciated.
↧
verilog-A to .lib translation in PSpice
Hey,
I have the following verilog-A coded component that defines a simple nonlinear function:
// VerilogA for memr, memr_f, veriloga
`include "constants.vams"
`include "disciplines.vams"
module memr_f(vp,vn,vout,vref);
electrical vp,vn,vout,vref;
parameter real vth=1,vo=1,Io=1e-9;
real vd,id;
analog begin
vd = V(vp) - V(vn);
if (vd>vth) begin
id = Io*(exp(vd/vo)-exp(vth/vo));
end else if (vd<-vth) begin
id = -Io*(exp(-vd/vo)-exp(vth/vo));
end else begin
id=0;
end
I(vout,vref) <+ -id;
end
endmodule
I want to make this as a sub-circuit in Orcad. So, I wrote the below code and saved it as .lib and created a new library with a new part with ports vp, vn, vout and vref.
.SUBCKT memr_f vp vn vout vref
.func vd() {v(vp)-v(vn)}
.func id() {IF(vd >= 1.0, 1e-5*(exp(vd/0.1)-exp(vd/0.1)), IF(vd <=- 1.0, -1e-5*(exp(-vd/0.1)-exp(1.0/0.1)), 0))}
Is vout vref {id()}
.ENDS
When running this, I get an error 'File does not exist' and when I click ok, I get 'Ocad contains an invalid path'. I want to know if there are any errors in the netlist I wrote which is equivalent to the above verilog-A code. Can you help me in this
↧
Generating 274-X and Lines&Text are not being included (but are included in ODB++ output)
Hi All,
This is very strange.
I have defined Films that include Lines & Text Elements. When I view the Film in the normal editor, all is visible. When I generate ODB++ all are visible and present. But when I generate 274-X, they are missing! All none Line and Text items are present.
The Lines all have a width of 0.2030, the text uses a long time used Text_Block.
The Lines and Text in question are being used to document the PCB.
↧
Export Constraints to be read in a spreadsheet
Has anyone had any tried or had any success doing this? I'd like to be able to see the constraints in a particular design without having to open Allegro. You'd think it would be a simple to export into Excel.
↧
↧
Correct specific rotation angle...again
In Allegro/Orcad PCB standard, 16.6 S064 have the following annoying problem: Have number of components which I left in previous PCB version in fraction rotation angles rotation: 269.996 degrees (90.003 / 0.005 / etc. - because probably I've done spin with cursor at 0 deg. rotation). I simly cannot Zero this fractional angle!
It is like 20 components from 200, but it is annoyng, especially for manufacturing. I try to resolve this by selecting component Move/Spin/Rotate, choosing Absolute / 270 / Body center and all possible combinations of Absolute/Relative and different rotation points, and even "iangle" in command prompt, but without success. Done this in General Edit or Placement mode. Only way to fix this currently is to unplace component and when place it again fractional part is reset. But it takes a lot of time.
It is either I am doing this wrong or I missing something into rotation concept.Obviosly I cannot also move the component to any specific angle - it always stays on 'moved angle.fractional angle'. Any advice or specific command I can use? Can it be something from design parameters, etc.?
Thanks in advance - I am asking this question for second time, and first time left the board as it was, but now there will be new revision, so I want to finally fix it and learn how to do this. Or place/unplace all these components and route them again.
↧
Footprint of QFN package
Hello,
I want to make pcb footprint of QFN-28(Cp2102) package. But I am getting problem while making through package symbol wizard. there is no option for QFN package. so can you please tell me which package i chose for this.
these are the e2 and e1 in the package symbole wizard PLCC/QFP parameters.
Also what will be the default padstack to use for symbol pins?
↧
Footprint of DB9 Connector
Hello Everyone,
I want to make the footprint of female DB9 connector. I don't know how to make this. can someone please tell me how to make this using Package symbol wizard??
I also want to make the footprint of 0548190519 (USB On-The-Go (OTG) Mini-B Receptacle, Right Angle, Through Hole Solder Tails andShell Tabs, Lead-free). Please someone tell me how to make footprint using Package symbol wizard??
↧