Hi,
Please help on the below error:
#1 WARNING(SPMHNI-316): Property warning detected.
WARNING(SPMHNI-301): Problems with component 'C4'. Error with component property '' and value 'VOLTAGE': '100VDC'.
I'am using Design Entry HDL and PCB Editor 16.6. I have been using the same HDL Library but first time to encounted the error on VOLTAGE.
Please help.
Thanks!
Hi,
I have setup a "System DSN" (I've also tried "User DSN") database via windows (C:\Windows\SysWOW64\odbcad32.exe), which uses my Microsoft Access database file. Then I selected that DSN and generated a .dbc file from the "Options > CIS Configuration" and used that as my configuration file.
However, when I attempt to Place Database Part, I can see all the tables in my database but I cannot see the parts inside the tables. I have also tried using the default "C:\Cadence\SPB_16.6\tools\capture\samples\BENCHACC.DBC" database sample with the same result.
Any suggestions?
Thanks!
In Concept 16.3 and before I have created a number of programs that take advantage of the ASCII csa files of a schematic. I edit these files and then re-generate the other schematic page files such as pagex.cpc, pagex.csb and pagex.csv.
However due to the new structure for 16.5 and above this method is not as straight forward.
I still use Concept 16.3 to regenerate the files via a batch file but I have added a new additional step to use the Csnetlister command to uprev the design to 16.6
At the moment I have not seen any issues with this approach but I am concerned that there may be issues I am not aware of.
Are there any pitfalls to using the process I have outlined above for future 16.6 designs?
Are there any changes coming in the structure of the sch_1 folder that would stop this process from working?
Has anyone else had similar problems and if so how did you solve them?
I started a new job, where they are using Cadece/Allegra/Orcad 16.3. I've laid my own boards out for 20 years and using several different programs but never Orcad. I'm having some troubles figuring out how to do simple things in the PCB.
I need to create a part, its a DC-DC converter AGF700-48S30LT. I need 3 different hole sizes. I've gone through the wizard and just normally but I can't seem to figure out how to add a pin. It appears that pins have to have their own file/drawing, so I created some hole files (this seems insane to me but it seems to be how it works). I created the pins through Tools>Padstack>Modify Design Padstack then right clicking on the pad and selecting edit. This let me create pads.
However when I create the pad if I keep the name the same it will modify all the pins rather than just one. Through the wizard it created 2 pin types one for pin 1 and one for all the other pins. But I need 3 pin types.
I've tried adding a pin, by selecting Layout>Pins then I select click somewhere, and I get the message No padstack specified.
Also I can't seem to change the pin numbers. I've double clicked on yellow number text and right clicked and nothing.
I've searched for videos on how to create parts in orcad 16.3 and I haven't found one that does it from scratch. Is there some resources out there?
Hi all,
I have received Gerber files from my manufacturer that can't import them to Allegro? They are edited version of my Gerber files which I had sent them for fabrication. They have applied some modifications on them and returned them to me to confirm them. When I tried to import them into Allegro PCB I received an error message indicating the lack of art_param.txt file in the search path!. If put that file from my original generated Gerber files. I can't see anything after import:
I'm wondering if anyone has any thoughts on the best way to communicate Variant BOMs to contract manufactures. Take for instance an arbitrary Resistor, R100, which is 10K Ohms in the base design. We may have one variant that uses a 10K resistor there and another design that uses a 2.2K Resistor in the same R100 location. Currently, we use the variant editor to set this up, and when we post-process the BOM to put it into a clean format, what we do is show something like the below:
Model A | Model B |
|
| ||
Populate | Do Not Install | Populate | Do Not Install | Value | Description |
R100 |
|
| R100 | 10K | Resistor, 0805 |
| R100 | R100 |
| 2.2K | Resistor, 0805 |
I know that this is confusing, but I'm not sure of how to make it not confusing.
Thanks for any input.
Hi,
I work with Orcad Layout 16.0.
I have a very big .DXF file (236 MB). I would like to import it and to convert it in a .MAX file.
As the file is too big, it is impossible to convert it, the program crashes.
Do you know a solution ?
Best regards.
Hello Folks,
I am using OrCAD PCB Designer Professional Version 16.6-2015 S061 (v16-6-112EW) [11/9/2015] Windows 32. My OS is Microsoft Windows 7 Professional 6.1.7601 Service Pack 1 Build 7601 64 bit.
When I try to click on the "Place Manual" button in the Place toolbar, nothing happens. The Placement dialog simply does not appear. I can select Place Components Manually from the Main Menu but the toolbar button does not work at all.
Is this a bug? Is there a setting I can use to fix this? I am totally stumped.
Thanks,
Allan
Hi all,
I have a problem with Cadence 16.6 version. When I select some symbols in sch, it is not highlighting in PCB. Actually I recently shifted to Win 8.1. Before that It was working on Win7 Perfectly. I have double checked in the capture intertool communication box is already checked.
Kindly Help.
Best Regards
Hi guys.....I'm using 16.6 Pro and manually placing test points. I have two connectors that have a dym. copper shape between them and need to add a test point for it but using the manual icon only allows me to do it to a track/cline or via. I thought I did this a few pcb's back but now I cant figure out how to do it. I read the Allegro manuals and checked this site. Any ideas how its done?
Thanks!
Hi All,
I have a schematic that has extra properties that I did not add:
CONNWIDTH 8.000
HIGHLIGHT NO
MAXWIDTH 8.000
MINWIDTH 8.000
NETGROUP 0
NETWEIGHT 50
PLANELAYERS
RECONNTYPE STD
ROUTELAYERS
SPACINGBYLAYER
TESTPOINT NO
I did not add these properties and I think they are interfering with the properties that I do use:
MAX_TRACK_WIDTH 30
MIN_TRACK_WIDTH 30
REC_TRACK_WIDTH 30
I am using powernet to create a net list. If I examine the netlist that is created the properties that I do want are not there for many of the nets. For the nets that do not have these extra properties seem to be OK. I am using powernet V2.0b07 and Orcad version 16.6 s055
Thanks in advance.
Roger
Hi,
May I know how I can setup/name those extended nets (XNet) in the schematics editor?
what I'm currently doing is my manually group and edit them in Constrain manager (physical).
Is there anyway where I can edit on Schematic capture so it automatically available when I moved to PCB editor later on.
Pelase advice.
regards
Kumar
Does anyone know where I can get the latest version of Powernet?
Thanks
Dear Community,
Version - SigXplorer - 16.6
My basic requirement is to analyze sata2.0 lines - 3 Gbps from Xilinx Artix 7 FPGA for which I have received IBIS-AMI Models. I am very new to this and I am confused.
1) The way I have started is that I have taken the IBIS Model and converted them to DML Model
2) Now for experimenting I have made a small topology which I am attaching here and I have assigned DML models to inverting and non-inverting buffers for outputs as well as inputs.
3) Now when I try and do Channel Analysis - It shows the following problem:-
4) Is there some problem with the IBIS Model or where is the problem?
Can someone please help me in this? I know this may be very silly mistakes on our part.
(Please visit the site to view this file)
I have attached the IBIS Model as well.
Regards.
Hello all,
I'm running OrCAD 16.5 and am having a problem generating an Allegro netlist. Creating a Tango or ComputerVision format netlist works fine. The Allegro netlist operation fails with the following messages for all simple parts:
#1 ERROR(ORCAP-36003): Conflicting values of following Component Definition properties found on C10 and C1 for part "CAP_SMT".
PCB Footprint
VALUE
C1 gives this error for C2 through C11.
3 180-REG-001644 CAP_SMT 4.7uF CC1210 10% 16V C1,C6,C7
8 180-REG-001618 CAP_SMT 0.1uF CC0402 10% 16V C2,C3,C4,C5,C8,C9,C10,C11
I've been using OrCAD since about 1987, so am fairly comfortable with the product. However, I haven't tried to generate an Allegro netlist for several years.
I'd appreciate any pointers as to what is causing this error, and if there is a solution I can implement.
I'd prefer not to delete all of the properties I've added, as they help with the BOM generation in Excel.
Thanks in advance for any recommendations.
Cheers,
Ralph
Hi All,
Is that possible to check, silk to solder mask overlapping in Allegro itself?
Do we have any constrains or option for that?
Hi!
I'm trying to import a dxf file in pcb designer 16.6, but dxf import menu doesnt open. I just installed it on this machine. On an other computer its works fine. Can it be solved somehow, or i should try to reinstall it?
Regards,
Sanya
Hi,
I don't know how to use properly this software can someone help me please to create a component and explain me how to route a board.
Thanks
Regards
I have the OrCAD 16.2 suite and files that someone else made that I would like to edit. I can open the schematic in Capture and the PCB (.brd file) in PCB Editor, but do not know how to link the two so that I can make changes on the schematic and update the PCB accordingly.
Can anyone provide step-by-step instructions on how to do this?
Thank you.
Is there any way to save a symbols to a library with padstacks that have been changed in the pcb design. If seems to only save the with the original padstacks.