Quantcast
Channel: Cadence PCB Design Forum
Viewing all 5525 articles
Browse latest View live

Unable to place component using ICA

$
0
0

Hello,

After setting a local database, I would like to be able to add component from the Internet Component Database (ICA).

First issue, when I click the ICA tab, an empry pop-up opens, there is no error code or message, just the following pop-up:

After clicking OK and the Go/ICA Home Page, I'm able to search for a part as expected until I chose one:

I can't see any Schematic Image  and I get a WARNING(ORCIS-6085) when trying to place the part:

Can anyone explain me how to solve those issues ?

Thanks in advance,


PCB Editor 16.6 parts placement annoying

$
0
0

Dear community,

I'm a real beginner so sorry in advance.

I completely designed a voltage conditioning schematic on Capture CIS, I created some parts for a LEM LV25-P and 2 connectors not having the footprints. Additionally I designed the footprints of those new components on PCB editor.

When I come to place the components on PCB editor I find really annoying to place only my designed parts because of a not-correct placing. When I drag one of those components through PlacementEdit it holds far away from my mouse pointer. 

I really don't know the reason. Please help.

Roberto

Gerber does not agree with allegro dimension. Everything is shifted

$
0
0

Hi,

I haven't seen this or ever been mentioned to me that the gerber does not agree with my allegro dimension.

Anybody sees this kind of problem before and what is your solution for this.

I have Allegro 16.6 - hotfix 67 which is the latest. I use CAM350 to verify the off set and the board vendor also told me so.

Thank in advance.

Regards,

TiBo

How to create a compressed BOM in Design Entry

$
0
0

I am using the Allegro PCB Design Entry HDL and I have a compiled and annotated schematic.

I can output a BOM that has a separate line for each part in the schematic but I need to collate each part number and total each part so that I get a series of lines with a different part number on each line:

Part1, 3, R1, R2, R3

Part2 , 4, C1, C2, C3, C4

Part3 , 1 C10

etc

How do I set up the template to create such an output.

Experience using Team Design Option in DE HDL

$
0
0

Does anyone have any experience using the Team Design Option in Allegro Design Entry HDL? We have used it on two projects now with mixed results. I would be interested in hearing from other companies that have implemented the tool.

Some specific areas of interest are using NetGroups and the version rollback feature.

Thanks,

Steve

Clines randomly refuse to snap to pin or segment vertex.

$
0
0

I am trying to get a cline to snap to a pin but it just does not connect.  The nets are the same but the wire just bounces around the pin.  After a whole lot of farting around, the net connects!  AARRGGHH!!!!  I try gridless routing, smoothing on or off, bubble on or off and the behaviour is just not predictable.  Sometime I can RMB snap to pin and it works, other times it doesn't.  Sometimes I can grab the rat and somtimes it is totally elusive.  What am I doing wrong?

Batch edit properties of a library?

$
0
0

Is there any way to bring up the table/spreadsheet of all the parts in a library to perform batch edits? Similar to when editing a schematic, how you can select a bunch of components and right click -> edit properties? (photo below for reference).

I can't find a way, but I feel like it has to be there.

For instance, If I wanted to add a new property to all components in my custom library, would I have to go through each component individually?

Unable to open .sch file in Orcad Lite 16.6.

$
0
0

I have a .sch file generated from Questa Prime (Mentor).

I am trying to open it  with ORCAD so that I can edit the same. However, when I follow the below steps all I get is a text file describing signal names, color, orientation etc. with no errors.

How can i view the symbol file in ORCAD? Kindly provide suggestions

Sample of text file is shown below:

WindowType IncrementalSchematic
DesignChecksum e7ZGO96?4RMXzCKPOfV3?0
RoutedNets {}
RoutedInst {}
WindowPreferences {showhierarchy 1 showacttime 1 inoutlocation 1 selequivnets 0 hidebuffers 0 hidecells 1 hideinverters 0 selectenv 1 autowave 1 lognets 1 popupenabled 1 mouseoverenabled 1 showdunames 0 showinstnames 1 shownetnames 0 shownetnamestyle corner shownetstate 0 showpinnames 1 showripindices 1 showvalues 1 verticaltext 1 netxFollowsControlLogic 0 netxMaxGates 1024 netxMaxLevels 32 use_code_preview 1 time0_warning 1 depth_warning 1 add_error_warning 1 diverge_warning 1}
EndOfStateInfo
# File saved with Nlview version 6.4.4_0 (04/08/25-18:45:38 bk=1.779)
#
property -reset
property autobundle 20
property boxcolor0 #00ffff
property boxcolor1 #999999
property boxinstcolor #ffffff
property boxpincolor #00ffff
property buscolor #ffff00
property closeenough 3
property enablebufferchaincollapsing 1
property enablescrollrect 1
property evaluateattrvalue 1
property extractsequentiallogic 2
property gatepinname 1
property inferbundlename 1
property instattrmax 50
property objecthighlight3 #00ff00
property objecthighlight4 #ff00ff
property objecthighlight5 #ffd700
property objecthighlight6 #0000ff
property objecthighlight9 #fa8072
property outboxcolor1 #a52a2a
property outboxcolor2 #000000
property outboxcolor4 #000000
property picksubnet 1
property pinattrmax 50
property pinorder 2
property recursivecallerrorlen 10
property searchvisibleobjects 1
property selectbycolor9 1
property showcellname 0
property showmarks 1
property shownetattr 4
property showripindex 3
property timelimit 50

module new v {} -nosplit
load symbol work.BUF_RCTL(fast) v HIERGEN portBus BUF_RCTL_SINF output.right 68 {BUF_RCTL_SINF[0]} {BUF_RCTL_SINF[1]} {BUF_RCTL_SINF[2]} {BUF_RCTL_SINF[3]} {BUF_RCTL_SINF[4]} {BUF_RCTL_SINF[5]} {BUF_RCTL_SINF[6]} {BUF_RCTL_SINF[7]} {BUF_RCTL_SINF[8]} {BUF_RCTL_SINF[9]} {BUF_RCTL_SINF[10]} {BUF_RCTL_SINF[11]} {BUF_RCTL_SINF[12]} {BUF_RCTL_SINF[13]} {BUF_RCTL_SINF[14]} {BUF_RCTL_SINF[15]} {BUF_RCTL_SINF[16]} {BUF_RCTL_SINF[17]} {BUF_RCTL_SINF[18]} {BUF_RCTL_SINF[19]} {BUF_RCTL_SINF[20]} {BUF_RCTL_SINF[21]} {BUF_RCTL_SINF[22]} {BUF_RCTL_SINF[23]} {BUF_RCTL_SINF[24]} {BUF_RCTL_SINF[25]} {BUF_RCTL_SINF[26]} {BUF_RCTL_SINF[27]} {BUF_RCTL_SINF[28]} {BUF_RCTL_SINF[29]} {BUF_RCTL_SINF[30]} {BUF_RCTL_SINF[31]} {BUF_RCTL_SINF[32]} {BUF_RCTL_SINF[33]} {BUF_RCTL_SINF[34]} {BUF_RCTL_SINF[35]} {BUF_RCTL_SINF[36]} {BUF_RCTL_SINF[37]} {BUF_RCTL_SINF[38]} {BUF_RCTL_SINF[39]} {BUF_RCTL_SINF[40]} {BUF_RCTL_SINF[41]} {BUF_RCTL_SINF[42]} {BUF_RCTL_SINF[43]} {BUF_RCTL_SINF[44]} {BUF_RCTL_SINF[45]} {BUF_RCTL_SINF[46]} {BUF_RCTL_SINF

Thanks,

Ansh


Automatic Capture.ini setup for database configuration

$
0
0

Hi,

I have a master INI file using the environmental variable "%CDS_SITE%/cdssetup/OrCAD_Capture/16.6.0/Capture.ini" that is loaded using the Capture INI manager here: http://www.orcadmarketplace.com/ProductDetails.aspx?ProductID=20.

When configuring a part database, the user's Capture.ini needs to be modified automatically to support the site database. For the database to work properly the following need to be modified in the INI file:

1) [Part Management] - no problems here, the site INI info is transferred into the user INI

2) [Symbol Selector Configured Libraries] and [Part Selector Configured Libraries] - the issue here is if "Number of Configured Libraries" isn't set in the site's INI but a "Library0" is configured, that library may not be transferred to into the user's INI. And if  the number is set, any changes the user made could be overwritten after Capture restart.

Anyone encountered this issue before? Workarounds? The only solution I could think of is set "Number of Configured Libraries=1000" and configure only "Library0" in the site's INI file. That way the user's INI will maintain any user added libraries.

Thanks for any help!

Error with netlist

$
0
0

Hello,

I want to create an electronic card as printed circuit with PCB editor.

I created my circuit in capture-orcad 16.6 with components that have footprints, but when I try to create the Netlist of my schema I get the following error. Will you help me to correct it?

 Best regards.

Exiting... "C:\Cadence\SPB_16.6\tools\capture\pstswp.exe" -pst -d "C:\USERS\ADMINE\DESKTOP\TEST\TP1.DSN" -n "C:\USERS\ADMINE\DESKTOP\TEST\allegro" -c "C:\Cadence\SPB_16.6\tools/capture/allegro.cfg" -v 3   -l 31 -s "" -j "PCB Footprint" -hpath "HPathForCollision"

INFO(ORCAP-32005): *** Done ***

Flip PCB design top to bottom

$
0
0

We have a complete PCB design that for manufacturing/production reasons we would like to flip the entire design top to bottom. The board was originally designed in Allegro.   Is there any way in allegro to swap layers top and bottom  and make this work? 

Cross-referencing between 16.6 Design Entry and Physical Viewer

$
0
0

Hi,

We know that the main design menu can open the schematic and PCB editor simultaneously and then it is possible to select an item on the schematic and it highlights on the PCB editor.

But is there a setting that allows the schematic and physical viewer to be opened simultaneously and to provide the same cross-referencing as with using the PCB editor?

Coupled Microstrip Model Modifications

$
0
0

Hi, I am using Allegro SigXplorer. For a simulation, I need to modify the coupled microstrip model, just by adding a three layer dielectrics in between the copper top and copper bottom (three different dielectrics). How can I do this?, I tried just by putting the coupled microstrip model in the canvas, selecting it and managing the layerstack but it doesn't work. Thanks in advance

CDS_A0_1 AnalogOutput and SigXplorer?

$
0
0

Hello

I would like to know how to use the CDS_A0_1 AnalogOutput model from the SigXplorer library but there is no associated topology part to add in the canvas. Where can I find an example?

Regards

CDS_A0_1 AnalogOutput

$
0
0

Hello

I would like to use the CDS_A0_1 AnalogOutput model from the SigXplorer library but I found no topology part (no element) to add in the canvas. Where can I find an example?

Thanks in advance

Regards


Starting a new project?

$
0
0

Not sure if this is the right place for this, but a beginner with this program could use some serious help, with perhaps the most basic part. I have the free versions installed and can access the program, but how do I start a new project in PSpice? Would greatly appreciate any quick responses for this question.

drill/excellon

$
0
0

I'm trying out a new offshore board house and they say:

"checked the file, only with drill holes positions, but without excellon layer, could you add the excellon layer"

I've sent a drill file as I always have with others. Anyone have an idea what I may be missing?

Node floating with transfo edited in ''magnetic part editor''

$
0
0

Hello,

I keep receiving the same errors when I try to simulate.

I created a transformer with the help of «magnetic part editor»

This is the transfo:

* Generated by Magnetic Parts Editor on Mon Mar 28 02:39:54 2016
.subckt 49925UC V_IN1 V_IN2
+ V_OUT11 V_OUT12
+ PARAMS: Np=14 RSp=0.00340928 LIp=4.73106e-006
+ Ns1=10 RSs1=0.00273003 Gap = 0
L_LP NLP V_IN2 {Np}
R_RP NRP NLP {RSp}
L_Leak V_IN1 NRP {LIp}
L_LS1 NLS1 V_OUT12 {Ns1}
R_RS1 NLS1 V_OUT11 {RSs1}
K_K2 L_LP L_LS1 1.0 core_model_K1
.model core_model_K1 AKO:core_model CORE (GAP={Gap})
.model core_model CORE (LEVEL = 3 OD = 30.84 ID = 0 AREA = 6.45 GAP = 0 Br = 1100 Bm = 5000 Hc = 0.175 )
.ends 49925UC

And this are the errors:

ERROR(ORPSIM-15142): Node N00141 is floating

ERROR(ORPSIM-15142): Node N00134 is floating

ERROR(ORPSIM-15142): Node X_U1.NLP is floating

ERROR(ORPSIM-15142): Node X_U1.NRP is floating

For now the circuit is really simple. But I would like to make it work before adding it  to a bigger project

Thank you!

Tom

Node floating error while using transfo of «magnetic part editor» (Orcad_16.6_Lite)

$
0
0

Hello,

I keep having the same problem with this quite simple simulation.

I edited the transformer with the help of «magnetic part editor».

This is the transfo given by «magnetic part editor»:

* Generated by Magnetic Parts Editor on Mon Mar 28 02:39:54 2016
.subckt 49925UC V_IN1 V_IN2
+ V_OUT11 V_OUT12
+ PARAMS: Np=14 RSp=0.00340928 LIp=4.73106e-006
+ Ns1=10 RSs1=0.00273003 Gap = 0
L_LP NLP V_IN2 {Np}
R_RP NRP NLP {RSp}
L_Leak V_IN1 NRP {LIp}
L_LS1 NLS1 V_OUT12 {Ns1}
R_RS1 NLS1 V_OUT11 {RSs1}
K_K2 L_LP L_LS1 1.0 core_model_K1
.model core_model_K1 AKO:core_model CORE (GAP={Gap})
.model core_model CORE (LEVEL = 3 OD = 30.84 ID = 0 AREA = 6.45 GAP = 0 Br = 1100 Bm = 5000 Hc = 0.175 )
.ends 49925UC

And this is the errors:

This is the circuit I would like to simulate:

Thank you for your help!

Tom

Global Allegro.cfg file

$
0
0

Hello,


I found an article that claims you can create a global allegro.cfg file and store it on a read only area of a server.  Then all that is necessary is to place the file path in the capture.ini file.  Does anyone know if this is true and if so what part of the ini file would this path go?

http://www.flowcad.ch/cms/upload/ApplicationNotes/FlowCAD_AN_Capture_2_PCB_prop.pdf

Thank you

Viewing all 5525 articles
Browse latest View live


Latest Images

<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>