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ERROR(ORCAP-36071): Illegal character "Dot(.)" found in "PCB Footprint" property for component instance.........

March 31, 2016, 12:09 pm
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So I open an existing .dsn in OrCAD Capture version 16.5 and proceed to make a PCB out of it. The OrCAD on my computer was a recent installation. The project and schematic are from 2 years ago.

Annotation seems to work:

INFO(ORCAP-1378): LAST USED REFERENCES [blah blah blah component references....]

INFO(ORCAP-1379): Done updating part references

Design Rules Check gives only a couple trivial warnings:

Checking Electrical Rules
WARNING(ORCAP-1829): Possible pin type conflict blah blah blah

Checking For Single Node Nets

Checking For Unconnected Bus Nets
WARNING(ORCAP-1595): Two wires/busses of different nets intersect visually, yet nets are not connected blah blah blah

Unfortunately, Create Netlist... produces about 80 of the following errors in the netlist.LOG:

Illegal character "Dot(.)" found in "PCB Footprint" property for component instance............................

Illegal character "Forward Slash(/)" found in "PCB Footprint" property for component instance..............................

Property "PCB Footprint" missing from instance.............................

Pin number missing from Pin "1" of Package..................................

#87 Info: PCB Editor does not support Dots(.), Forward Slash(/) and White space in footprint names. The supported characters include Alphabets, Numerics, Underscore(_) and Hyphen(-).

If I select all components in the schematic and look at Properties... the PCB Footprint column cells typically have content like this: RAD/.200X.100/LS.100/.031 or are blank. So, this is an example of the '.' and '/' that the netlist generator doesn't like.

Library Verification/Correction doesn't seem to do anything.

I can't Back Annotate because I don't seem to have any .SWP that it wants.

If I look at the properties of a component in the schematic OrCAD typically tells me ERROR(ORCAP-1733): Allegro footprint AX/.400X.100/.034 was not found in the search path.

If I go and Place Part, the design cache and DISCRETE.OLB libraries open. If I select a part from the DISCRETE library that doesn't exist in my design and place it and Edit Properties... the PCB Footprint is always blank, no matter what part or from what built-in library. And these are the built-in Cadence libraries and parts, NOT something I created myself. So how come Cadence removed the PCB footprints from all parts and rendered their product useless?

If I fill in the PCB Footprint cells with something acceptable to the netlist, OrCAD will go ahead and create a .brd file, but what Allegro shows is just empty space. If I try to Place parts, it complains it can't find the footprint specified in the Properties.

OK what am I doing wrong here?

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DRC ERROR LINE TO SHAPE SPACING

April 1, 2016, 11:29 pm
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hey,

i am using orcad16.6 .  I made PCB in orcad pcb designer. I create gerber file that TOP.art and BOTTOM.art but when i import this file in PCB designer I got the DRC ERROR "Line to Shape spacing" Constraint value 5 mil and actual value 0 mil . I changed constraint value to 0 mil but still i got the same error . i cant understand what to do . Please any one can help me

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Recommend the stackup and layers for HDI PCB

April 2, 2016, 11:17 am
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I am designing the PCB for BGAs at double side.


I think that it will need to use HDI PCB.
It is first time to do HDI PCB design.

It is difficult to decide the layers and stackup.

I am considering about the following spec.

- 3 + N + 3 type stackup, 10 ~ 16 layers.
- stacked microvias

Please recommend the the layers and stackup by your experience about HDI PCB design.

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diode breakdown current

April 3, 2016, 6:40 am
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Hello, I´m looking for a way to use an equation as a reversed diode current after breakdown. I tried editing the model paramters of the diode, but the result wasn´t exact what i need. And I have a problems after the breakdown with a voltage controlled current source. Is there a way to put an equation like ID=1/(1-(Vin/VBreak)^N) into a diodemodel?

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Create custom VAC-Source in pspice

April 3, 2016, 6:47 am
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Hi, I'm a beginner in pspice.

I have a bad signal that I could measure and put into an excel table. I want to create a filter and watch the reaction of the bad signal to it. How can i generate a custom source from a signal i measure?


How can I define my own source from a data-file - e.g. excel.

thanks

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DRC Troubles. Same net spacing. Thermal connects

April 4, 2016, 1:12 am
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Hello everyone!


I got stuck with two troubles in Allegro PCB.

Look at the figure. The line between SMD and Throu hole pad was made manually. DRC show an error, because the clearance between the line and the copper pour less than 20 mil. I don't know how to convince the Allegro to increase this clearance. Of course, I can do it manually by adding Voids. But I reckon if Allegro pours a copper automatically, it have to follow its rules automatically also.

The second 'bug" you can see below. Allegro made the thermal connection and broke his clearance rules. And it didn't show violation! I got the question from manufacturing company about clearances!

Is that "bug" of Allegro? Or I did something wrong?

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PCB design software for Linux machine

April 6, 2016, 11:22 am
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Hi,

We currently have SPB16.6 Installed on our Linux server, However, it seems inconvenient to use:

1. The design environment isn't integrated; the user has to first run Allegro HDL to create schematic, then run the PCB editor to create layout. This meens that forward/back annotation is inconvenient.

2. Also, there seems to be a lot of set-up to be done before actual design work starts.

3. Lastly, for every foot-print or library edit there are separate tools that must be loaded separately and break the design flow.

Is there any way to use SPB as an integrated design environment? If not, what other alternatives do we have? Am I missing something?

Since my group's research focus is IC, our PCB needs are usually simple (~2-4 layers, High freq but not to dense designs)

Thanks ahead,

Matan

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Re-numbering pins

April 6, 2016, 3:01 pm
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I tried searching the community, but couldn't find the answer to this. I'm new to OrCAD and having trouble figuring out how to do some of the simplest tasks. I'm using PCB Editor V.16.6.

In this case, I'm creating a custom footprint for a 640 pin connector. The pattern for the footprint includes pairs of rows that are offset from the neighboring pairs of rows vertically (by exactly one pin spacing). I had no problem creating the pads and placing all 640 pins correctly. I was using the matrix tool available on the options pane, so each time I placed a pin, it was placing 2 in the X and 8 in the Y for a total of 16 pins. I continued on like this, and meticulously entered the coordinates for each of these blocks of pins. No problems so far.

The problem starts when I try to re-number the pins. I'm starting at the bottom left corner and increasing pin count vertically and then to the left. The renumber pins dialog window seems to make sense and should do what I want, but, because columns are staggered vertically by one pin spacing, it will start to label the first two columns from bottom to top, but at the top of the columns, it skips a number because in the third column there is a pin that is one position higher than in either of the first two columns. Then, when it gets to the third column, it skips a number at the bottom because the first two columns have a pin in the lowest position, but the third column does not. The number that it skips is where there would be a pin (if the footprint were a perfect matrix) but there is no pin because of the staggered spacing of the columns. It continues on in this manner until it reaches the end of the footprint, but because of the skipped numbers, it finishes on 719 instead of 640.

So, when I'm creating a device file for the footprint, I specify that it has 640 pins, which is fine. When I try to read that device in to a BRD file (via a netlist where every pin is connected to a single net) then it will read in the netlist up to the first 640 pins, but pin # 641 creates an error because the device isn't supposed to have that many pins. In actuality, the device doesn't have that many pins, it's just that some of the pin numbers got skipped by the auto rename pin function. So now I can't assign any pin# higher than 640 in the netlist, even though the pin #s go up to 719.

I guess my question is, how can I keep the auto rename pin function from skipping pin numbers just because my footprint isn't a perfect square matrix? Do I have to go in and manually rename each of the 640 pins myself? If so, why is there an auto rename pin function in the first place? Any help would be appreciated.

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Issue with duplicated Pspice model -Full version of Cadence 16.5

April 7, 2016, 12:20 pm
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Hi ! We are trying to implement a full bridge inverter with two NCP5181 as showed in the figure. When we copy this half bridge model with the same inputs, eveything works well. When we are trying to invert the two logicals inputs (DSTM1 and DSTM2)on the second half bridge, nothing works. Any thoughts ?

Thank!(Please visit the site to view this file)

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Issue with duplicated Pspice model -Full version of Cadence 16.5

April 7, 2016, 10:08 am
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Hi ! We are trying to implement a full bridge inverter with two NCP5181 as showed in the figure. When we copy this half bridge model with the same inputs, eveything works well. When we are trying to invert the two logicals inputs (DSTM1 and DSTM2) on the second half bridge, we have 0V at the output of both circuits. Any thoughts ?

Thank!

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Orcad Capture: how to set "find" in entire design by default or all the times

April 8, 2016, 12:35 am
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Normally I have to select design and then use "find" option to search any item in orcad capture. If one/more pages are selected then it will search only in that pages.

Is there any possibility to set "find" in entire design by default?


Thanks for your supports in advance.

BR

Reja

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constraint manager : missing MIN_LINE_WIDTH while import dcf file

April 8, 2016, 2:08 am
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Is dcf file import/export safe for setup constraint rules?

I try to export dcf file, change the min width constraint of a net , and import the dcf file back.

But the value of min width does not recover to the value before, why?

My tool version is PCB SI XL, 16.6, S054

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Minimum blind/buried via stagger distance

April 9, 2016, 12:59 am
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Hi,

I'm using a BGA package controller having 0.5mm pitch and 0.3mm ball dia. I'm getting DRC error named "minimum blind/buried via stagger distance whenever i try to place a via on SMD pad of the controller. I'm using blind via which connects layer 1 to layer 3. There's no error if i place via away from the pad. But i can't do that to pins since its a very tight layout. How can i avoid that DRC error???

Any help would be appreciated.

Regards,

Arun

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Footprint trace / net names

April 11, 2016, 8:40 am
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Pictures below show a footprint with suggested fan out supplied by the part manufacturer. Prior to importing the netlist, the traces all have net names that start with $$$followed by a number that has no correlation to the actual pin number. I'm assuming that this is a place holder name for the "real" net name that is loaded with the netlist.

For future reference, how would I make one of these parts for times when one is not available from the manufacturer?

Tom

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I have no folders in the artwork control form, and cannot add any subclasses to the film folder, with PCB editor ver 15.7

April 12, 2016, 11:59 am
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15.7 was operating fine on an XP system, we moved to a faster win7 (pro) machine.we upgraded to 16.5 then 16.6 all functioned fine.

we needed to use 15.7 for a certain client, and reloaded it on the win7 machine.

any help is appreciated,

Thanks,

Tom

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Displaying Additional Component Properties on Silkscreen?

April 14, 2016, 12:09 pm
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Is there a simple way that I can display manually added properties from a schematic symbol on a footprint? For instance, if I have a 3 position jumper such that has 2 positions, whose properties are  "POS_A" (pins 1-2) and "POS_B" (pins 2-3), can I set up the footprint such that there is silkscreen text that if I fill in POS_A as "VDD" and POS_B as "GND" in the schematic, when I go to place the footprint these texts are attached to the footprint?

I know I could do this manually on a board to board basis but I'm guessing there is a very simple answer I'm missing.

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Error 6245 and 6250 when creating CIS Bill of Materials

April 18, 2016, 7:56 am
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Hi,

I'm not able to create a BoM using CIS as I used to before I created my own component database.

When trying to, I get the following pop up message and log, and a empty excel file is opened.

Can anyone help me solve this problem ?

Thanks,

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Adding block diagrams to the ORCAD schematic

April 18, 2016, 3:07 pm
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Hi 

I use Google sheets to generate block diagrams. Will they import into Orcad Schematics? This would be my second page of the schematic after the title page

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Regarding PCB Nets visibility in Layers.

April 19, 2016, 6:21 am
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Hello all ,

         I have a 6 Layer PCB , i want to select some particular traces  and want to hide the other traces on the same layer . The traces i was selecting were routed in inner layers also .

Also i want to print the selected traces  by hiding the other traces  . 

Can any body please help me , how to  do this in Cadence 16.6 .

Regards ,

sarat.

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Where can I get a 220x233 VME card template?

April 19, 2016, 6:24 am
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I need a 220mm by 233mm eurocard template for a project. We are using OrCAD PCB Designer Professional and I see that if I choose

Place>Manually then choose Library, I get two options in the mechanical symbols window, one for a EUROD and one for a EUROS.

Does anybody know where I can get the outline for the 220 x 233 VME card?

Also, does Cadence provide a site where we can download other ready-made PCB outlines for other standard card types?

Mark

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