Refering to this thread 
I would like to ask if someone still has this conversion tool and could mail it? I mailed this mentioned Steve, but mail bounces back (no wonder after 8 years).
Any help how to view .BD1 files using Windows is also welcome.
Thanks!
Hi,
sounds a silly one, but .... i own a PCB Editor suite 16.3, works well. Now I saw the recent offer for a new capture 17.2 license.
Being a self-employed consultant, upgrading all the suite to 17.2 is a bit expensive, unless there is a strong need for it.
I am just wondering if Capture 17.2 would still be able to interface seamlessly with my PCB Editor 16.3 ?
Any known limitations ?
regards,
Jacqes
Hello,
I'm working on a PCB that must be updated from the schematic, I didn't make the first version of this board and I had to create a Symbol library from the existing board, some of the components are new, so I had to make them, but when I try to import the new changes into the layout, it removes all the components and I have to re-place them, this creates a ton of extra work. Is there a way to import the schematic changes without having to start from scratch on the placement.
Attached is a plot of the settings I'm using on the schematic.
Thanks in advance
Hi,
I have a design in which i have to use different line widths. During routing, in the option tab's line width drop down there are so many unnecessary line widths are showing. I want to clear all these like we purge unused padstacks. Is there any way to clear this drop down panel. Kindly help.
Regards
Hi,
I have a design in which some nets should be rout with variable width. Like a net in some regions have 0.1mm width, same nets in some other regions have 0.2mm width. I want to know that is there any way to toggle between two widths during routing instead of going every time to the line width drop down. Kindly help.
Regards
On the Hotfix_SPB17.20.005_README_CCR.txt file, you can read the following text: "1588769 ALLEGRO_EDITOR UI_GENERAL ALT+key shortcuts are not available in 17.2".
BUT this problem are NOT FIXED ! NOT fixed also on the next HotFix releases 006 and 007 !
Need to press at least 2 time the ALT key and WAIT some time, for enabling "FILE" anf others menu, but the sub menus features not responding as required ! There is a very big problem to use shortcuts, and for activate menus ! In the 16.6 release ALT+key there is NOT a problem.
A workaround or solution are very welcome. If you have please share it !
Thanks, Gianni.
I am looking for suggestions before I purchase orcad.
I see there are several library functions/ options
Which one are people using? either 16.6 or 17.2
ICA -
Local Part Data Part
Place Part
Thank you
Is there a way to compare changes between two .brd revisions? I would like to overlay layers from two different .brd files (or gerber files) and have the differences highlighted. Thanks for any help.
Hello!
Wondering if someone might have advice on how to fix this issue I'm seeing. I have a custom pad shape that when placed on the PCB the ratsnest (and therefore trace) do not connect in the correct location.
Note the attached image showing ratsnest connecting to middle of pad geometry, however, there is no pad there to connect to.
Here's the part with the trace routed (again, note the incorrect connection point).
(please note all images of the part on the bottom side of the pcb).
I've modified the design padstack to have the origin of the pad and stop mask to be the thicker portions of the pads, however, it had zero impact on the connection point. Is there a way to fix this?
I've attached the pads and parts in the zipfile. Also, as a reference this is the part I'm using http://www.bourns.com/docs/Product-Datasheets/SRR6038.pdf
(Please visit the site to view this file)
Greetings,
Due to the first time use of allegro pcb editor, could anyone guide me for doing the following:
1. How to add via that connects to specific internal planes (I am designing 6-layer board) ?
I have created vias that each one connects top layer to each internal layer respectively. And I have them added to "physical constraint set" in the "constraint manager". I don't know how to place them on .brd design
environment. How to make a via that passes a internal plane but not connect to it (I know anti pad, but not really know how to apply it)? When place such via in .brd design, how to visually see whether the via is
connected or not to a internal plane.
2. How to add wire connection through a plane layer but not connect to the plane layer?
3. Could tool development group issue a detailed user manual that can help NEW user? I have seen video tutorials and some documents on the web, but not really detailed or complete.
I have been learning this tool for weeks and did not have much progress by using the resources on the web, if any one could be contacted directly for question it would be greatly appreciated. Please let me know.
My email is cheng.hao@okstate.edu
Any help will be deeply appreciated. Thank you for your time.
Regards
Cheng
Can someone please explain the difference between "Add Rect" and "Shape Add Rect"?
Hi.
I did a search of the forums for this, but have trouble believing I'm the only one seeing this.
My Capture CIS is telling me that it's out of date at 17.2-2016-S006, with 17.2-2016-S007 being available. This is despite the fact that I've installed two hotfixes since then. It should be showing as 17.2-2016-S008. I searched through the READMEs and found nothing that seems applicable.
Any thoughts would be greatly appreciated :)
Cheers,
M
I am new to PCB Design.
While designing PCB, I updated the 100 mil pitch 6 pin connector to 50 mil pitch 6 pin connector.
I observe the Vcc_3.3V pin (1st pin highlighted in the image) antipad is all over the connector pins instead of only on at the first pin.
The DGND pin (6th pin) antipad is also getting highlighted like Vcc_3.3V Pin.
Even though there is no DRC error, I feel there is some kind of mistake near the connector.
If anyone is familiar with this, kindly let me know.
Pad Dimensions
Drill - 26 mil
I have three questions that are related:
1. If I create net classes in Allegro using CM, is there a way to highlight these net classes in the schematic?
2. To speed creation of net classes in CM, is there a way to highlight nets in schematic and then assign the highlighted nets to a net class in CM?
3. In lieu of #1 and #2, is there a way to create net classes in schematic that will get carried over to the board file and CM? (In a previous life I used PCAD 2000, which had a very intuitive way of dealing with net classes that addressed all of my questions here. I would be surprised if Allegro didn't have similar functionality.)
It is very tedious making notes of auto-assigned net names and then assigning them to net classes.
I am currently using Allegro version 16.6 and Design Entry CIS.
I'm running into an odd problem. I have two pins on an SOIC-8 that are next to each other and tied to the same net. I'm trying to lay a dynamic shape over the two pins to connect them together along with some pins on some other parts close by. For some reason, no etch will form between the two pins when I cover them with the shape. What I can do is create a small shape between the two pins. That works until I try to merge the two shapes together. When I do that the shape between the pins disappears. It doesn't seem to be a constraint manager issue. Any suggestions?
I used to change the funckeys on ealier version and save it on the ENV file . Can't do that anymore . I have to enter them in the command window. But when I restart the app , I need to do it again to have the funckeys back . I there ways to save them ??
Hello,
For a design I use a couple of the same circuits. In the schematic they are drawn as Hierarchical blocks. The circuits consists of a BGA with some resistors and capcitors. For the first circuit I use Place replicate create. Afterwards for some circuits I use Place replicate apply. Now I need to mirror half of the circuits on the same layer. For Example BGA U1 has resistor R1 placed on the left side. The placement of BGA U2 needs to be mirrored so that resistor R2 is placed on the right side. Can someone explain how to?
With Place replicate apply I can rotate and mirror the placement to an other layer, but I can't mirror it on the same layer. Maybe there is an other function that I don't know about?
I've got a design with multiple hierarchical blocks and already placed components in the layout. Now I want to swap some connections in only 1 block. Is there some way to disconnect 1 hierarchical block from the others so it basically doesn't link to the others anymore? Because I already already placed some componets, I would prefer if it's possible to preserve the refdesses.
I tried making a new schematic that I later on convert to a hierarchical block in TOP LAYER schematic. (where you can see all the hierarchical blocks) In this schematic I copy all the components from the block I want to convert, but the refdesses automatically change. Even when I use Options / Preferences / Miscellaneous / Preserve reference on copy. This function only works when you are working on the same schematic page?
The only way out I know at the moment is by copying the schematic and changing refdesses by hand.
I use Cadence Capture/Allegro version 16.6-p005.
Edit: I found something over here I'll try that first.
Edit2: the solution suggested in the link above is only for simple Hierarchy designs and not for complex hierarchy designs. So it doesn't work for me.
I ended up editing formpath thinking it was the path to my format symbols. It ended up breaking OrCAD PCB Editor.
It is great that within the Pad Editor 17.2-2016 we can define a different X and Y Tolerance on Slots (Thank you very much).
However, how, using PCB Designer 17.2-2016, do we have the additional column show up within the Drill Legend? I am only getting one of them.
I should also see both of them in the Drill Customization Window, but I do not.
I expected that the "Tolerance" and "Tolerance2" within the .dtl file would give me the two Columns required, but they did not.
Has PCB Designer not caught up with Pad Designer?