Today I installed latest patch #85 and what I can see this problem with white screen is fixed.
I can now work with my window maximized.
Br Johan
Today I installed latest patch #85 and what I can see this problem with white screen is fixed.
I can now work with my window maximized.
Br Johan
Hi Forum ,
I have a set of off-page connectors as follow
I want to change the names and directions from a spreadsheet (Similar to export/import properties) . If I Ctrl+E the off-pages connectors I get the following
How can I export/import the last table ? Since I have ~200 off-page connectors , I rather manipulate them from a spreadsheet
Thanks
I want to add step packages to parts in the library so I don't have to map these each time.
If I do from the library, is there a shortcut to see them placed on a PCB, so I can verify the XYZ?
I've stumbled into a rather dense board layout with several painfully placed via fanouts in place. I now need to replace the vias with slightly smaller padstacks due to density and spacing issues.
I can not locate the mode/function to interactively change the via padstacks on the already placed and routed fanouts! I have found references to such a mode and operation in user guides, but none apparently work for the PCB editor (apparently only the router). I DO NOT want to spend hours painfully deleting and re-doing the fanouts to get smaller via padstack selections. None of the "mode change_via" commands appear to work.
I'm running Allegro "Performance" Editor 16.6 hotfix 64. If anyone can educate me on how to "change vias" I would be extremely grateful. (Yes, I've "unfixed" the via fanouts that get implemented by default,. so I can manually slide and edit the traces one by one. I've also edited the CM to allow smaller via padstacks and such).
Thanks in advance!
With 17.2's creation of an unfilled shape on Board Geometry/Design_Outline subclass when loading a .emn file we have lost the line draw that was being created with the older versions of Allegro. I was copies of that line draw to represent the board's outline for various other purposes, eg. solder mask, paste mask, nc route path.
Is there a way to generate from the border of an unfilled shape a continuous line draw? The line draw could end up on any other subclass, I have no preference.
Just another obscure challenge that I haven't faced before. I want to create an SMD symbol with a funny shaped pad and an array of drill/vias for thermal connectivity to inner layers. Also want the inner layers to connect with solid non-thermal connections to like-net planes. Again, I'm confused by reading the user guides.
Somewhere the symbol editor guide says you have to define "pads" for connectivity to the bottom and inner layers for the tool to figure out what to do. But I don't really want "pads" on the inner layers, especially one large enough to encompass the entire array of drills that I've defined. I would prefer that the drill holes just connect individually with solid connections to same-net planes or isolation spaces to other-net planes and shapes. So far, I have a large bottom layer pad and "null" inner layer pads defined on the symbol.
The symbol looks OK when placed on a board and I finally got the drill holes to "show up" on the layout display and 3D viewer. It appears as if the drills pass through the inner same-net planes as well as the other-net planes and shapes but with no visual indication of connection or isolation to any of them.
Short of running artwork to see what's connected, is what I want even possible? Also, I haven't been able to find the correct "mode" to assign the "Pin_Dyn_Thermal_Con_Type" property on the symbol, as mentioned elsewhere in the forum.
Thanks in advance for any expert guidance!
Hello everyone,
I am using Cadence Allegro PCB Designer 17.2 for designing a PCB board. The software worked well for many days as I progressed till the last part of my design.
Recently, when I was finishing up things, I ran a DRC check through the path"Display > Status > Update DRC". The software ran a multithreaded DRC and closed abruptly. No changes were saved in the file after my previous saved session.
Secondly, when I tried adding "aperture" files using "Artwork Control Form" window, the following error appeared. However the board file gets saved, all the Allegro software windows close abruptly.
"The program has encountered a problem and must exist. The design will be saved as a .SAV file that can be recovered by using a dbdoctor (if applicable). To resolve problem, first obtain the latest software update from Cadence and if the problem persists contact Cadence Customer Support. In addition to the data Cadence support requests: please provide the MiniDump files found in the folder: "C/Cadence/.... ".
The artwork window is not allowing me to add aperture files. Just to add more info, I had designed the board in "mm" and to create artwork files, I had to change the units from "inch" to "mm", which gave me a warning of loss of accuracy, which is not a matter of concern for my design. I wonder if this mismatch is the cause of above errors.
I would like to mention that these problems are occurring for only this particular board file.
The software is working absolutely fine for other board files, is able to update DRC and create artwork files.
It would be great if someone could help, suggest about what exactly is going wrong in the board file and how these issues can be rectified.
Thank you !
Regards,
Rahul
Hi
I am trying to setup my database(.mdb) file using the Configuratiuon Wizard in OrCAD CIS 16.6
aFTER completing the Setup wizard the CIS Explorer is showing the Data Source Name and Parts are displayed in the Parts Window but when i click on the parts, i do not get any Symbol Drawing and cannot transfer them to my design either.
Is t0here something to do with the path?
This is how the tool has always worked for me, but the question was proposed to me and I’m not sure how to react. When generating dynamic shapes around square padstacks (we typically will use a square to denote Pin 1 of a connector), the keepout area in the dynamic shape is set based on the spacing constraints. However, the keepout shape maintains the shape of the pad, just increased by the constraint distance, when really the corners could be rounded and/or chamfered and still keep the same copper to copper spacing.
See the image attached, the shape keepout should be able to follow the diagonals.
Is there a setting that can control this that I am not aware of?
Hi Cadence Experts.
I been using Cadence PCB Editor for years for board layout but with recent development, i need to cater footprint and symbol creation, schematic entry as well.
I do not know where to start like.
1. How will the geometry(design entry use) will link to the footprint(PCB editor)? what files or paths do i need to set up?
2. What are the parameters needed to insure i can use the latest version from the central library rather than the ones present in my board.?
3. Can you please help what other files path are needed to be properly set up in order for the process to run smoothly.
Your help will be greatly appreciated.
Does anyone else noticed this?
Do you know how to fix this?
Thanks in advance.
Jan Pieter de Ruiter
Honeywell CCP
hello,
I am new to ORCAD and Pspice simulation.
I am trying simulate a mux ic.
but while simulation I am getting following errors-
ERROR(ORPSIM-15113): Model Sw used by X_U1.S0 is undefined
ERROR(ORPSIM-15113): Model Sw used by X_U1.S1 is undefined
ERROR(ORPSIM-15113): Model Sw used by X_U1.S2 is undefined
ERROR(ORPSIM-15113): Model Sw used by X_U1.S3 is undefined
ERROR(ORPSIM-15113): Model Sw used by X_U1.S4 is undefined
ERROR(ORPSIM-15113): Model Sw used by X_U1.S5 is undefined
ERROR(ORPSIM-15113): Model Sw used by X_U1.S6 is undefined
ERROR(ORPSIM-15113): Model Sw used by X_U1.S7 is undefined
ERROR(ORPSIM-15108): Subcircuit 5e-9 used by X_U1.XU1 is undefined
anyone help me to resolve the issue.
thanks and regards
DC
Capture has decided to delete many of the ports I have for some reason:
Since the cavity for an embedded component is based on the Placebound shape in the package file (according to the Embedded Component Design Best Practices document), and Package Keepout areas are not meant to be placed at the package level, how can I establish minimum Placebound-to-Placebound spacings for an individual component at the package level that will show up as DRCs during placement? Do I need to use a DFA_Bound shape and then develop a DFA spreadsheet with the spacings I want? I was hoping to set it at the package file level and forget about it.
I'm new to Cadence and working through a part creation process for a common library accessed by multiple users.
I see a blog question earlier on something similar but I'm just wanting to see if I'm heading in the right direction with what I'm doing.
First I create a padstack and use that in creating the PCB footprint. When I need to combine that with a schematic symbol into a part I choose the library that I want the new part to reside in and open it in Capture then right click on it in the file tree and select Add New Part. In doing that I can create the part schematic symbol as well as assign the footprint to it that I created earlier and save it back to that library for use.
I'd just like some advice on whether this is the best process to create parts using only Capture CIS and PCB Editor without implementing a separate option like PCB Librarian right now. Please relate a better process for me if possible based on your experience.
Thanks for any comments.
Kevin
All, I have capacitors, resistors fanned out and tied to symbol (MARKED) for ease of Move/Routing.
I need to change parts with same footprint. After I import Logic, the "Marked" fanouts go away.
I can "Unmark" the offending fanouts, then run and all is well. Unfortunately, this is NOT the solution we are looking for.
Any ideas would be appreciated. TIA, Patrick
I am having problems with page numbers (and total number of pages) that appear in the title blocks. Although they are sometimes correct, most of the time they are wrong. I know how I can fix them manually but I have not been able to find out a method of automatically updating these properties to the correct values. Any suggestions?
I am using 16.6 and my design has hierarchical blocks.
I have also not been able to find information on where the title block pulls this information and when it is being updated. Sometimes the total is updated in the title blocks of all pages, but sometimes not. Also, what is the placeholder text for these fields? For that matter, is there a list of recognized placeholders and the source of the information that they are substituted with? (Aside from <title> and <doc> that are from the design template.)
Many thanks!
Yanko
Hello,
**** 02/14/17 18:00:57 ****** PSpice 17.2.0 (March 2016) ****** ID# 0 ********
** Profile: "SCHEMATIC1-74LV4052 NEW" [ D:\dc workspace\orcad\74lv4052 new-pspicefiles\schematic1\74lv4052 new.sim ]
**** CIRCUIT DESCRIPTION
******************************************************************************
** Creating circuit file "74LV4052 NEW.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS
*Libraries:
* Profile Libraries :
* Local Libraries :
.LIB "D:/dc workspace/downloads/orcad library/switchana.lib"
* From [PSPICE NETLIST] section of E:\Orcad172\Cadence\SPB_Data\cdssetup\OrCAD_PSpice\17.2.0\PSpice.ini file:
.lib "D:\dc workspace\downloads\new library\nom.lib"
*Analysis directives:
.TRAN 0 1000ns 0
.OPTIONS ADVCONV
.PROBE64 V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))
.INC "..\SCHEMATIC1.net"
**** INCLUDING SCHEMATIC1.net ****
* source 74LV4052 NEW
R_R1 N00541 GND 999k TC=0,0
R_R2 N00187 GND 999k TC=0,0
R_R3 N00194 GND 999k TC=0,0
R_R4 N00206 GND 999k TC=0,0
R_R5 N00221 GND 999k TC=0,0
V_V1 N00499 GND 5Vdc
V_V2 N00508 GND 3.5Vdc
V_V3 N00423 GND 5Vdc
V_V4 N00589 GND 1.5
V_V5 N00577 GND 2.5Vdc
V_V6 N00565 GND 3.5Vdc
V_V7 N00553 GND 4.5Vdc
X_U1 N00423 GND GND N00589 N00577 N00565 N00553 N00541 N00187 N00194
+ N00206 N00221 N00508 N00499 GND GND 4052A
**** RESUMING "74LV4052 NEW.cir" ****
.END
WARNING(ORPSIM-15223): Library file "D:\dc workspace\downloads\orcad library\switchana.lib" has changed since index file switchana.ind was created.
WARNING(ORPSIM-15227): The timestamp changed from Tue Feb 14 17:39:21 2017 to Tue Feb 14 18:00:52 2017.
INFO(ORPSIM-15422): Making new index file switchana.ind for library file switchana.lib.
Index has 31 entries from 1 file(s).
ERROR(ORPSIM-15461): Incorrect number of interface nodes for X_U1.
what can be the probable issue.
Regards
DC
Hello,
I am using below written model for simulation but its giving the error-ERROR(ORPSIM-15108): Subcircuit 1000E-10 used by X_U1.XU1 is undefined
.Subckt 4052a A B INH yio0 yio1 yio2 yio3 ycom xio0 xio1 xio2 xio3 xcom V+ Vss Vee
* Optimus for full simulation of 4052. Symbol 4052B.asy
XU1 A B INH Y0 Y1 Y2 Y3 VDD Vss 2TO4 VDD={Vcc} SPEED={Vel} TRIPDT=1000E-10
XU2 xio0 xcom Y0 V+ Vee CD4066
XU3 xio1 xcom Y1 V+ Vee CD4066
XU4 xio2 xcom Y2 V+ Vee CD4066
XU5 xio3 xcom Y3 V+ Vee CD4066
XU6 yio0 ycom Y0 V+ Vee CD4066
XU7 yio1 ycom Y1 V+ Vee CD4066
XU8 yio2 ycom Y2 V+ Vee CD4066
XU9 yio3 ycom Y3 V+ Vee CD4066
.Ends 4052a
*
.SUBCKT 2TO4 A B INH Y0 Y1 Y2 Y3 VDD VGND vdd1={vdd} speed1={speed} tripdt1={tripdt}
.param td1={1e-9*(475)*5/{vdd1}*{speed1}}
.param td2={1e-9*(375)*5.0/{vdd1}*{speed1}}
*
XIN1 A Ai VDD VGND CD40_IN_1 vdd2={vdd1} speed2={speed1} tripdt2={tripdt1}
XIN2 B Bi VDD VGND CD40_IN_1 vdd2={vdd1} speed2={speed1} tripdt2={tripdt1}
XIN3 INH INHi VDD VGND CD40_IN_1 vdd2={vdd1} speed2={speed1} tripdt2={tripdt1}
*
AINH INHi 0 0 0 0 ENA 0 0 BUF tripdt={tripdt1} td={td2}
AA Ai 0 0 0 0 An Ap 0 BUF tripdt={tripdt1} td={td1}
AB Bi 0 0 0 0 Bn Bp 0 BUF tripdt={tripdt1} td={td1}
AY0 An Bn ENA 0 0 0 Y0i 0 AND tripdt={tripdt1} td={td1}
AY1 Ap Bn ENA 0 0 0 Y1i 0 AND tripdt={tripdt1} td={td1}
AY2 An Bp ENA 0 0 0 Y2i 0 AND tripdt={tripdt1} td={td1}
AY3 Ap Bp ENA 0 0 0 Y3i 0 AND tripdt={tripdt1} td={td1}
*
XOUT1 Y0i Y0 VDD VGND CD40_OUT_1X vdd2={vdd1} speed2={speed1} tripdt2={tripdt1}
XOUT2 Y1i Y1 VDD VGND CD40_OUT_1X vdd2={vdd1} speed2={speed1} tripdt2={tripdt1}
XOUT3 Y2i Y2 VDD VGND CD40_OUT_1X vdd2={vdd1} speed2={speed1} tripdt2={tripdt1}
XOUT4 Y3i Y3 VDD VGND CD40_OUT_1X vdd2={vdd1} speed2={speed1} tripdt2={tripdt1}
.Ends 2TO4
*
.SUBCKT CD4066 1 2 3 4 5
* 1 ANALOG INPUT
* 2 ANALOG OUTPUT
* 3 CONTROL
* 4 VDD (POSITIVE SUPPLY)
* 5 VSS (NEGATIVE SUPPLY)
*
RINP 3 11 500
CINP 11 5 4P
D1 11 4 D1
D2 5 11 D1
*
M1 12 11 4 4 MP3U L=3U W=10U AD=768P AS=768P PD=208U PS=208U
M2 12 11 5 5 MN3U L=3U W=4U AD=256P AS=256P PD=80U PS=80U
*
M3 13 12 4 4 MP3U L=3U W=30U AD=3600P AS=3600P PD=900U PS=900U
M4 13 12 5 5 MN3U L=3U W=10U AD=1080P AS=1080P PD=286U PS=286U
*
M5 14 13 4 4 MP3U L=3U W=150U AD=256P AS=256P PD=80U PS=80U
M6 14 13 5 5 MN3U L=3U W=50U AD=128P AS=128P PD=48U PS=48U
*TRANSMISSION GATE DEVICES
M7 2 14 1 4 MP3U L=3U W=1500U AD=4500P AS=4500P PD=3000U PS=3000U
M8 1 13 2 20 MN3U L=3U W=500U AD=2500P AS=2500P PD=1000U PS=1000U
M9 1 13 20 5 MN3U L=3U W=8U
M10 20 14 5 5 MN3U L=3U W=8U
M11 20 14 1 4 MP3U L=3U W=32U
*
.MODEL MN3U NMOS LEVEL=3 VTO=1.0 TOX=5E-8 NSUB=1E17
+XJ=1.5U LD=0.3U KP=40U RD=5 RS=5 CJ=3E-4 CJSW=3E-10
+KAPPA=1 THETA=1E-4 ETA=1.4 GAMMA=1.1 VMAX=4E5
*
.MODEL MP3U PMOS LEVEL=3 VTO=-1.0 TOX=5E-8 NSUB=3E15
+XJ=0.7U LD=0.3U KP=18U RD=5 RS=5 CJ=1.8E-4 CJSW=2E-10
+KAPPA=.33 THETA=4E-2 ETA=0.6 GAMMA=0.6
.MODEL D1 D IS=923.17E-18 RS=10 CJO=1.0000E-12 M=.3333 VJ=.75
+ ISR=100.00E-12 BV=35.357 IBV=10U TT=5.0000E-9
*
.ENDS
*
what can be the probable issue ,and How to solve the issue.
Regards
DC
I'm going to ask a stupid question: can someone explain the purpose of the six subclasses (Assembly, Cavity_Outline, Display, Pastemask, Place_Bound, Soldermask) for embedded components (Embedded Geometry)? The help documentation only really discusses the purpose of the cavity outline. I understand the other subclasses as they relate to surface components, but I'm not sure how they were meant to be applied differently to embedded components.