Allegro: How to set the clearance between two grounding plane

August 31, 2017, 1:53 am

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Hello all.

Right now I have a board. I want to add two grounding planes, one at top, one at bottom. My aim is going to set the gap to be 15 mil ( also known as clearance). I worked with KiCad for sometimes before, and it lets you to enter the clearance value when creating the copper-filled grounding plane. But how to do it in Allegro? Any suggestion? Thanks.

And by the way, I have a very simple circuit with just a few resistors. But when I try to connect them together, I got DRC error on every traces I added. It all says, 'line to line spacing. Actual value:0' or 'Max neck length. Actual value: 0'. I have no idea why they came out. I really could use some help here. Thanks again.

Smith

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single layer pcb

August 31, 2017, 7:47 am

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I'm trying to create a single-layer flex pcb in allegro and cannot seem to delete the second layer from the cross section editor. Am I missing something obvious? (Allegro 17.2)

Custom Pad Shape with Multiple Openings in Solder Paste

September 6, 2017, 7:02 am

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We are working with more QFN packages, which all have the center pad. On almost all datasheets they recommend the stencil design for the solder paste on this center pad to be an array of multiple openings to make sure that a) not too much solder is applied and b) it is well distributed over the surface of the large pad.

I tried to create a custom pad, but cannot as I am only allowed ONE element in the shape.

Since this type of stencil design is now "common place" how is this being supported inside Allegro ?

e.g. of this from the TI CC2650 datasheet

How do I rotate a component to 24deg ? (Using version 16.6)

September 6, 2017, 10:21 am

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How do I rotate a component to 24deg ? (Using version 16.6), seems to be stuck in a multiple of 45deg mode, so do I need a different version of Allegro?

Schematic: Changing Path of All Items in Design Cache

September 12, 2017, 8:55 am

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I am working on a schematic project with 100+ unique parts, and the design cache each has the path to the source library, i.e.

• PART1 : PATHA\LIB-A
• PART2 : PATHB\LIB-B
• PART3 : PATHB\LIB-B
• PART4 : PATHA\LIB-A
• PART5 : PATHC\LIB-C
• PART6 : PATHB\LIB-B
• PART7 : PATHB\LIB-B

Now, I need to change the LIB-B Path from PATHB to PATHX. Do I need to individually "Replace Cache" for each part sourced from LIB-B? Or is there a way to "replace lib" for all items in LIB-B? 

Allegro incorrectly displays line width

September 12, 2017, 9:01 am

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I'm designing PCB in Allegro version 16.3. I set the line width as 20 mils for routing nets, however, the width of 20 mils lines display same as other (for example 4 mils line in the below image).

I copy my design to other laptop, it is ok, the 20 mils lines looks wider than 4 mils lines.

Could someone help me to address this problem?

Unable to delete out-of-date shape items (URGENT Cannot Create Artworks without fixing this)

September 12, 2017, 10:12 am

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After updating shapes, I get a number of "Out of date shapes"

Clock the color button next to them gives me a list with coordinates, if I click on coordinates view is moved but there is no shape or boundary there.

I used: Shape->Check

Click on shape => Shape checking completed.... 2 problem pts found
the outline of the problem pts is visible on the screen
I can select them while in the check mode

** I cannot access them in anyway outside of check mode to delete (or merge) them

I have run Database Check with all options ticked, it states no problems

URGENT: The whole design is now stalled until this can be fixed.

In Allegro 17.2 and previous versions, In the "CONNECTOR" Library of the OrCAD software, the Pin4 and Pin6 positions of the "CON18A" component symbols are wrong.

September 18, 2017, 1:36 am

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In Allegro 17.2 and previous versions,

In the "CONNECTOR" Library of the OrCAD software,

the Pin4 and Pin6 positions of the "CON18A" component symbols are wrong.

Will this problem be fixed in later releases?

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Allegro16.2 issue?Softaware exit from working enviorment.

September 18, 2017, 10:28 pm

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Program has encountered a problem and must exit.

Change the font in an entire design in Capture

September 19, 2017, 7:06 am

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Is there a way to update the font in the entire design all at once? I've already completed the design but the font size is causing issues when importing into Pro/e. I want to increase the font size of all the text.

Migration of a total design from OrCAD 10.3 to 17.2

September 19, 2017, 9:20 am

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Hello,

   We have recently addopted OrCAD PCB Designer (17.2). Previous designs were done in OrCAD 10.3 (capture and layout). I have seen examples on how to convert a .MAX file to a .BRD file, but I haven't been able to find a tutorial on how to migrate an entire design so I can mod it in 17.2. Does this exist? I am curious about updating a .DSN file tied to the new .BRD file. Where are the symbols/footprints located that are now associated with the new .BRD file? How can I get the intertool communications setup between the old .DSN and the newly imported .BRD file? I have been able to do a new design from scratch with the new toolset, but a complete design migration has been difficult at best. Thanks in advance for any guidance here. 

Can the size of Pin Numbers be changed ?

September 21, 2017, 5:19 am

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I am working with 0.4mm BGA and small DFN parts and the default pin number size is way toooo big, how can I change the pin number text size ?

Measure command is not popping up display window, 16.6

September 25, 2017, 12:21 pm

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When using display measure the popup window is not displaying, so I don't get a measurement.

Constraint Manager Design for Fab Mask Checks

September 27, 2017, 2:33 pm

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Does a good reference exist someplace detailing how to use the Constraint Manager Design for Fabrication Mask constraints that showed up in 17.2-2016 Hotfix 25?  I have created a DFFMaskCset, created a Mask subgroup that selects all of the soldermask subclasses (PkgGeo, BrdGeo, pin, & via) and applied the CSet to it, and I have enabled the Mask analysis modes.  When I run DRC, I get no errors related to the soldermask, even when I set the Slivers and Islands values to something ludicrous like 100mil.  The What's New in the Hotfix doc doesn't offer any wisdom beyond a little description of each setting.

Many thanks.

Place Replicate Module Is Not Including Route Keepout Areas

September 29, 2017, 12:32 pm

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Hi All,

I am trying to use the place-replicate feature to create some fairly complex multi-symbol modules with precise placement and routing on a multi-layer board.  I want to include a set of route keep-out areas on inner plane layers to void the planes underneath sensitive pins and signal routes.  I have created the master module and updated it to try and include the keep-outs, but it apparently doesn't work.  When I select and move the module to a different location, the keep-out areas stay put where they were.

Any ideas how to accomplish this? Otherwise I'm looking at many hours of tedious drawing!

I'm running PCB 16.6 (Hotfix 043, before I let my maintenance lapse).

Thanks in advance,

Roger

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PSpice Model Editor Default Settings

October 2, 2017, 6:11 am

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Hi,
Is there a way to change the default value of 27°C temperature in Model Editor when creating a new device by characteristic curves?
My datasheet curves are defined for 25°C but the Model Editor expects them at 27°C.
Any solution is appreciated.

Thanks

How to replace part in Orcad using TCL syntax "ReplaceInst"

October 3, 2017, 3:01 am

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Hi Group,

I am looking to change some components (out of many) to new library part. If doing so with Orcad cache then it will change all parts regardless of the reference designator. I tried to use below command with no success. Nothing happened in the Orcad. Moreover, below syntax does not contain old part field so I am not sure which part will get replace until it works.

ReplacePart(libName, pkgName, partName, device)

I also tried below command but Orcad flags error as " 1]No matching function for overloaded 'DboPage_ReplaceInst'". Appreciate if someone could shed some light on this code. I put so much time with below syntax without any success. There is no example given in the documentation as well. 

set src_pkg_name "CAPACITOR_NP"
set src_pkg_name [DboTclHelper_sMakeCString] 

set lib_part "LIBRARY.OLB/CAPACITOR_NP"
set lib_part [DboTclHelper_sMakeCString] 

set device [$lPlacedInst GetDevice $lStatus]

$lPage ReplaceInst $lPlacedInst $src_pkg_name $lib_part $device $lStatus 0 0 0 1

Specctra Router in SPB 17.2 with ISR 026 will not Quit

October 3, 2017, 9:46 pm

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Hi Folks,

Installed a trial of Cadence SPB 17.2 with hotfix 026 in Windows 7 (64-bit) Professional.  Everything working well and even Specctra, except for one thing.  When you hit the quit button or Exit from menu, Specctra generates another entry dialog.  Every time I hit the Quit button, it moves the entry dialog to a shifted position, but DOES NOT nor will not exit the program!  Every other application in the Suite works perfectly!

Now here is the funny part...I use VMware Workstation 14.0 (latest and greatest) with a Windows 10 (64-bit) Professional environment, and the SPB 17.2 installation work perfect there including Specctra.  The only difference I can figure is the VMware version is hotfix 025 while the hotfix in Windows 7 is 026.  I tried updating the Windows 10 version in VMware, but that still works OK.  Something SPB 17.2 does not like about Windows 7?

CT

Cant see Allegro PCB designer in product choice

October 4, 2017, 2:43 am

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Hi 

Earlier my product choice dialog box was this

But now, it never shows Allegro PCB Designer product in dialog box. as shown below.

I dont remeber what i ve done. i think once i was done reset license cache. thnks for help in advance.

Is it possible? Reference designation tricks needed

October 4, 2017, 2:34 pm

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Is it possible to setup the Reference designator assignment so to add prefixes?

I will have a multi-page design some of this pages will make a block of the system.  And I want that Resistors from lets say page 1 to 6 get a prefix on its reference designation like RA1, RA2. . . RA345, then from pages 7 to 10 RB1, RB2 . . .RB245 etc.  I don't want to use hierarchical design at the moment.  

Is this possible? 

Thanks!