Quantcast
Channel: Cadence PCB Design Forum
Viewing all 5525 articles
Browse latest View live

Unable to open link http://www.cadence.com/html/orcad/start/


[17.2] PCB Designer crashes every time DRC is run

$
0
0

Hello everyone,

I recently moved to 17.2 but I'm running into a problem.  For a certain design the application will crash without any errors or notification if I run the DRC.  Strangely enough it only does this when I am using one of my designs(IE .brd file).  If I use a different design it doesn't crash.  

Does anyone know what could be causing this?  It's very annoying because it also locks the licence file so I have to wait a couple of hours for the licence use to be reset.  

Thank you,

Dylan

Orcad Capture - save project as not working

$
0
0

Hi,

When pressing on the  "save project as" button a blank window with no options appears - see figure below.

Any idea how to fix this?

I'm using orcad capture 16.6 with a dongle license.

Thanks,

Amitai

Reduce clearances/thermal relief between shapes and clines

$
0
0

Hello,

I'm using allegro 16.6 and I'm having some difficulty with clearances between certain shapes:

From my screenshot, I'm trying to connect all the areas in red together (they are all RXGND). Is there something I should be using such as global parameters or some box i need to tick for these smd pads to be covered?

Cheers, 

Fraser 

Allegro Opens Last PCB File instead of File I click to open?

$
0
0

Let's say I have 2 PCBs, A and B. I work on A, save, close out of Allegro (17.2).... Then later, whether a few seconds, minutes, hours or days later, I go to open B, whether from the "pinned" menu on the app icon itself, or from the file location itself in Windows Explorer. Allegro loads, but opens A anyway. Once Allegro is open, I can use the "open" menu and find B in the explorer, and open it so it isn't the end of the world. But still, annoying. Has anyone seen this behavior, or better, found a way to solve it?

IPC-2581 Number Precision

$
0
0

I am exporting an IPC2581 containing the Cross Section Data only. I am having an issue with number precision. My cross section thickness values are defined in mils. One example is 1.775 mil. When I export the IPC 2581 the file converts this to inches and only retains the number to 5 decimal points of precision so I end up with 0.00178 which is inaccurate. 

I have searched though the menus and help docs but I cannot find where you can adjust this. I am using Allegro PCB Designer 16.6 Hotfix 93.

Any help would be appreciated. 

Thank You

Jonathan

Spacing C-set for shape instance

$
0
0

I need to draw a dynamic ground shape that has a larger clearance than the other ground shapes (same net name) on the board.  

Is there a way to apply a C-set to one shape instance, rather than by net class or region?

I tried assigning the Dyn_Clearance_Oversize to just that shape, but this has no effect.

Can I use BLOCK_NUM and subdesigns together?

$
0
0

We use hierarchical schematics extensively, and in this case I have large chunks of circuitry that I'd like to divide by an initial number in the ref des. For this I expect to use BLOCK_NUM in a custom ref des pattern like ($PHYS_DES_PREFIX)($BLOCK_NUM)[0-9](1).

Inside some of these hier blocks, there will be multiple instances of the same block. In this case, I want the ref des to be the same in each replicated block but add a the SUBDESIGN_SUFFIX to these ref des. Like usual, I would package each of these blocks using "Generate Subdesign" individually before packaging the design from the top using "Force Subdesign".

When all is said and done, I'd like to have ref des similar to the below examples:

R11: First resistor in BLOCK_NUM=1

C72: Second capacitor in BLOCK_NUM=7

U54B: Fourth IC in BLOCK_NUM=5 with SUBDESIGN_SUFFIX=B

D953K: 53rd diode in BLOCK_NUM=9 with SUBDESIGN_SUFFIX=K

The objective is to use the first number to group sections of circuitry. CPU, PHY, Ethernet, GPI, etc. This way, if it starts with a "1" I know it's a CPU part, and a "4" is power supply, for example. Helpful during design and manufacturing/servicing. For the suffix, that would indicate reuse blocks. If I have 3 GPO blocks, then they might use "C" through "E" as a suffix.

Currently, though, I'm not able to achieve this using these standard properties. It seems that BLOCK_NUM cannot coexist with subdesigns. The subdesign suffix is present but those parts don't get the BLOCK_NUM prefix to the numbers in the ref des. Is this possible?

I was able to get the desired results if I added PREFIX and SUFFIX properties to all blocks as desired, did not use subdesigns, and just packaged once from the top level of the schematic using the ref des pattern "($PHYS_DES_PREFIX)($PREFIX)[0-9](1)($SUFFIX)". However, I'm not sure if this is a good idea. Perhaps DE-HDL and/or Allegro will be unhappy if I try to pursue this method? It will still be easy to group these parts into clumps by their page number or ref des, and then using Placement Replication I find that I can still make use of modules to speed up layout.

Any feedback on this ref des concept and my strategies to achieve it?


Error when updating part status in part manager.

$
0
0

Hi,

Im using Capture CIS and our CIS  library is configured through Excel. every time im updating the part status i got this error message

Performing Status Update.
The timestamp of cached part package doesn't match that of OLB part package in {\\47.802.15.145\CLIB\SCH LIB\SCH_LIB.OLB}.
The timestamp of cached part package doesn't match that of OLB part package in {\\47.802.15.145\CLIB\SCH LIB\SCH_LIB.OLB}.

INFO(ORCIS-6274): ********************************************************************************

can you please explain whats the problem?. ive tried updating status on offline as well as online. but no use.

CIP component "Display Name" not displaying in Capture (UserField01)

$
0
0

We renamed some of the "UserField" properties.They display the new property name in CIP, but when viewed in Capture (CIS Explorer) the column displays "UserField01".

How do we fix this?

Package Geometry vs Board Geometry?

$
0
0

What's the difference?

I am creating a mechanical pin right now and i'm unsure which soldermask i should be using.

Cheers,

Fraser

unrotatable reference designator

$
0
0

Hi,

 Is there a way to set RefDes in component footprint to be always at 0deg (or even better: 0 or 90deg) no matter what rotation component has?

Regards

Kriss

Question on stackup

$
0
0

Newbie here. Looking for feedback on the following stackup from one of our designer.

- 4 layer PCB, original design stackup shown below

- PCB fab shop has concerned about asymmetric core design and recommended a balance design with 0.5oz copper across all 4 layers

- 0.5mm Core/Prep is also not standard, hence 0.46mm was suggested

- as a result of the revised stackup, a 35um finished copper,  ~10% increase in trace width was suggested

Need help on:

1. Is there an obvious problem with the current stackup?

2. Our designer does not want any change on trace width (RF application), what would be our options?

Thank you in advance!

Has the "capture image" command been removed from v17.x Allegro?

$
0
0

the command was in 19 of the 16.6 menu definition files, but not in any of the 17.2 menu definition files

D:\>
D:\>cd \Cadence\SPB_16.6\share\pcb\text\cuimenus

D:\Cadence\SPB_16.6\share\pcb\text\cuimenus>grep -il "capture image" *men
allegro.men
allegro_free_viewer.men
apd.men
apd_partition.men
apd_si_sigrity.men
cbdsymbol.men
chipiosymbol.men
icp_symbol.men
orcad.men
partition.men
pcb_symbol.men
sip.men
sip_partition.men
sip_rf.men
sip_rf_partition.men
sip_si_sigrity.men
specctraquest.men
sq_si_sigrity.men
xlibsymbol.men

D:\Cadence\SPB_16.6\share\pcb\text\cuimenus>cd \Cadence\SPB_17.2\share\pcb\text\cuimenus

D:\Cadence\SPB_17.2\share\pcb\text\cuimenus>grep -il "capture image" *men

D:\Cadence\SPB_17.2\share\pcb\text\cuimenus>

OrCAD Capture: "A Package with this name already exists" Error

$
0
0

I am using OrCAD Capture 16.6-S055.  In one of my designs, when I edit a schematic part (part editor, not properties spreadsheet), and attempt to change the name of the package, the part editor generates the error "A Package with this name already exists".  However, there is no such name in the design.  The name does not show up in the design cache and it does not appear in the object properties spreadsheet.  What's going on?


OrCAD Layout .MAX to .BRD (Allegro) OrCAD 17.2 . Conversion?

$
0
0

I am on OrCAD 17.2 and finding no choice to "easily" convert .MAX files to any layout format in Allegro. 

What is the recommended way to do this ?

There is no translation option in Import >  Translators > "   "

How do I go about this ?

No Graphics preview to see component footprint

$
0
0

I am unable to see graphics preview of component footprints in Allegro. However, I can see the text form of it. 

How can I see graphics ? 

Import Netlist to OrCAD PCB Designer 17.2 gives error but no description of Error

$
0
0

I have a good netlist from OrCAD Capture CIS, that I import using . Import > Netlist > Import Logic Type "Design Entry CIS(Capture), Place Changed Component "Always" > Import Cadence

which yields 

#1   ERROR(24) File not found
     Packager files not found

#2   ERROR(102) Run stopped because errors were detected

netrev run on Aug 28 17:59:59 2017

   COMPILE 'logic'
   CHECK_PIN_NAMES OFF
   CROSS_REFERENCE OFF
   FEEDBACK OFF
   INCREMENTAL OFF
   INTERFACE_TYPE PHYSICAL
   MAX_ERRORS 500
   MERGE_MINIMUM 5
   NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
   NET_NAME_LENGTH 24
   OVERSIGHTS ON
   REPLACE_CHECK OFF
   SINGLE_NODE_NETS ON
   SPLIT_MINIMUM 0
   SUPPRESS   20
   WARNINGS ON

  2 errors detected
 No oversight detected
 No warning detected

cpu time      0:00:12
elapsed time  0:00:00
--------------------

Any hint on what error 24 is ?

Thanks,

Ajeya

Allegro 17.2 Component Placement Problem

$
0
0

I am new to Allegro. 

I have a .MNL netlist generated from Capture CIS 17.2. On Import to Allegro 17.2, view log says netin imported successfully.

When I do Place > Component Manually > The list is complete with all the components in my schematics. However, I do not see any graphics in Quickview or any indication of presence of component. 

When I check-mark a component and move the mouse over to the Allegro screen, there is no component visible.

In the command line log, it says > Cannot Load Symbol 

How do I proceed from here ?

OLD properties Persist in ic selector window after querying

$
0
0

Hi,

I have configured CIS first time  with excel as the database. everything looks fine. when im querying on CIS explorer, no proplem. After that I've created new configuration file with Microsoft access as database. The new database contains entirely different properties from the old excel database. In both cases ive edited the Capture.ini file just editing the schematic part library directories. But after configuring, i opened Z(explorer),

1. I've used explore tab for searching components, then, properties from new database only are displaying in ic selector window. fine no problem.

2. when i used query tab, and searched. properties which are there in old excel database (not in new database. damn sure) are displaying along with properties from new database. from where it comes?. i ve attached the images.

PCB Footprint and Description are there in the new database also. thats y their values are shown i assume. Currently it doent make any problem. I want to know from where it comes?. am i done any thing wrong?

Thanks in Advance :)

Viewing all 5525 articles
Browse latest View live


<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>