OrCAD Capture Symbol and Multiple BOM Items

September 24, 2018, 1:24 pm

≫ Next: How to simulate a PCB with PSpice

≪ Previous: Xtalk simulation

$

0

0

Hi,

I am wondering if it is possible to have a Capture symbol be linked to multiple BOM items.

The example I have is a Battery Holder that uses two of the same contact clip for the Positive and Negative Terminals.

I want a single schematic symbol and footprint for this part, so that its dimensions don't have to be considered every time a new design is made.

For the BOM, this part should come out to QTY=2, for each placed Battery holder but it comes out as one because of the CIS/CIP linking. 

Anyone know of a solution or workaround?

Thanks.

---

How to simulate a PCB with PSpice

September 25, 2018, 8:18 am

≫ Next: Orcad Layout importing a .MAX file into footprint library

≪ Previous: OrCAD Capture Symbol and Multiple BOM Items

$

0

0

Hi folks

I watched tutorial on youtube but am still very confused with PCB SI. First of all, my UI looks different. I'm using Orcad PCB SI S038 SPB. Do I need a special license to enable simulation function?

I want to test a logic circuit with propagation delay. I know it can be done in capture but I need to test the exact PCB. I try to follow https://resources.ema-eda.com/ema-blog/how-to-perform-signal-integrity-analysis-on-nets-in-orcad-pcb-designer-professional only to end up at first step

Many thanks

Orcad Layout importing a .MAX file into footprint library

September 25, 2018, 11:16 am

≫ Next: Windows10 - Pad Editor crashes, everytime.

≪ Previous: How to simulate a PCB with PSpice

$

0

0

Hi, 

I'm working on a layout thats halfway done by a former engineer, and I cant seem to find the .LIB file or the footprints. I was thinking of making a copy of the .MAX file, renaming it, and then importing it into the library manager. However, I get an error saying "This design can't be edited this way. You need to edit it in the layout". I was wondering if it's possible to how to add .MAX files into the library manager so i can use the footprints from those components ?

Windows10 - Pad Editor crashes, everytime.

September 27, 2018, 12:13 am

≫ Next: How to create a title block?

≪ Previous: Orcad Layout importing a .MAX file into footprint library

$

0

0

Hello all,

Does anyone have any experience with Windows10 and Allegro 17.2 ?.

Basically we switched over to Windows10 this week and if I edit a padstack, it crashes..... everytime. I get the message that it has 'stopped functioning' with an option to close the program.

If I save... it crashes... If I update to design... it crashes... If I open a .pad directly OR open it by editing a padstack in a footprint... it crashes on save....... grrr !

I have a spare computer I am using to edit padstacks, Windows7 machine... but that's not a long term option !.

I did a complete fresh install of Allegro and have applied the latest patch (047)... nothing helps.

HELP !, is it a Windows10 error or is there a magic path or setting to fix this ?.

Thanks a lot guys,

Chris

How to create a title block?

September 27, 2018, 4:20 am

≫ Next: Model Selector question

≪ Previous: Windows10 - Pad Editor crashes, everytime.

$

0

0

Re-posting here as I initially posted my question in the wrong section of these forums.

Is there any guide on how to create a title block? I have been looking on the forums and googled it but I still have not found a clear explanation to do what I need.

I have inherited a title block that I would like to modify. When placed, the block auto-fills some fields, for instance the PROJECT, CURRENT PAGE and TOTAL NUMBER OF PAGES are filled and updated automatically, so that the block always shows "PROJECT= my project name", "PAGE YY OF XX" (where YY and XX are actual numbers.

Now, I naively copied the part using part-developer 17.2 and saved to a new library. This, alone, seems enough to break the nice field functionality and now the title block shows instead
"PROJECT= $PROJECT"
and
"PAGE $CURRENT_DESIGN_SHEET OF $TOTAL_DESIGN_SHEETS"

How do I fix this? What is the correct procedure to create those "magic fields"? And, more importantly, where is this all explained?

Many thanks in advance for any help.

Model Selector question

September 30, 2018, 2:29 am

≫ Next: Footprint Preview

≪ Previous: How to create a title block?

$

0

0

Hi,

Is there a way to invoke model selector during SI model device assignment in Capture?
It assigns using the first available model of the component.

Thanks

Footprint Preview

October 1, 2018, 10:20 am

≫ Next: OrCad Captur CIS - How to replace to a new Title block with while keeping the fields data from the current Title block?

≪ Previous: Model Selector question

$

0

0

Hi everyone,

I'm a newbie. It's the first time I use PCB Allegro.

I can't see the preview of any components, even Resistor or Capacitor.

And I don't know how to add library.

Please supporting me.

Thank you.

OrCad Captur CIS - How to replace to a new Title block with while keeping the fields data from the current Title block?

October 2, 2018, 8:37 am

≫ Next: flip-flop issue in Capture

≪ Previous: Footprint Preview

$

0

0

Hi,

I have a new Title Block that I want to update in my already existing designs.

Is there a way to replace the Title blocks while keeping the data in the fields from the original Title Blocks on each page?

Thanks!

---

flip-flop issue in Capture

October 2, 2018, 12:09 pm

≫ Next: Re-annotate Schematic after Layout

≪ Previous: OrCad Captur CIS - How to replace to a new Title block with while keeping the fields data from the current Title block?

$

0

0

Hi all

I'm running simulation which involves a flip-flop. Problem is the output of the flipflop stays low in this particuliar circuit no matter the input is. I checked the setting for CLR and CLK in datasheet and the flipflop works fine in any other circuits but this one. I did initialize it with 0 by set DIGINITSTATE to 0. Did I do it wrong or it's a bug? How do I solve it if possible?

I tried 7474 and 74175 and such but none of them work in this circuit

I find post with same problem. Now I start to think of it a bug o.O

Re-annotate Schematic after Layout

October 2, 2018, 4:47 pm

≫ Next: Allegro Design Entry Hdl PM Error

≪ Previous: flip-flop issue in Capture

$

0

0

I've designed a board, took it through layout, and then had to go back and make some changes.

Is it possible to re-annotate the schematic and have the REFDES for the components in allegro be updated to match? Whenever I rename a component in the schematic, and import the netlist in allegro I end up having to replace the parts.

Is there a way around this? Or am I just stuck?

Allegro Design Entry Hdl PM Error

October 5, 2018, 12:25 am

≫ Next: General Capture Questions - Symbol Rotation & Creation

≪ Previous: Re-annotate Schematic after Layout

$

0

0

this error is shown when a project is opened even if i am using libraries from local directory not from cds_site.

i am using Design Entry HDL 17.2 Hotfix S046.

Regards,

Jesh

General Capture Questions - Symbol Rotation & Creation

October 5, 2018, 9:07 pm

≫ Next: Capture .DSN - How to "replace" path references in the design cache and make them point to the design itself?

≪ Previous: Allegro Design Entry Hdl PM Error

$

0

0

Hi all, so some silly capture questions perhaps someone has insight they can share.

So my first question pertains to associating a PCB Footprint "aka .dra" to a capture symbol. How to do this without cutting and pasting the physical location and name of the dra file ? There is no browse button in the symbol editor..Cant seem to view the pcb footprint either... One other thing, how does one go about protecting the symbol so an engineer cant willy nilly change the footprint assignment. Basically I am trying to develop a standard library and once that library is created it's hands off for engineer edits.

Any clues ?

Next up is symbol rotation at the schematic level. When I rotate a symbol through 90 degrees the symbols attributes go all over the place. This thing cant even put the attributes back in the correct place going right through 360 degrees. I was wondering is there a switch or something to keep things lined up. I don't relish the idea of having to create both horizontal and vertical symbols, perhaps there is an easier way ?

Thanks

Paul..

Capture .DSN - How to "replace" path references in the design cache and make them point to the design itself?

October 7, 2018, 11:57 pm

≫ Next: Can not place ORCAD sch symbol

≪ Previous: General Capture Questions - Symbol Rotation & Creation

$

0

0

When working with a Capture .DSN, I often see how the schematic symbols in the design cache is referenced to various libraries some of which are gone or originates from a location which is no longer accessible or available. I have searched the help files in order to find a way to replace all those invalid paths with a definition that makes the symbols referenced to the design itself.

This is not "clean up cache" but merely "clean up paths".

Is there a way to do this? 

Can not place ORCAD sch symbol

October 8, 2018, 2:08 am

≫ Next: Gloss- center between pads not working

≪ Previous: Capture .DSN - How to "replace" path references in the design cache and make them point to the design itself?

$

0

0

Hi there,

we are using Cadence16.6, ORCAD  CAPTURE CIS. It works fine until yesterday. All of a sudden, I can not place sch symbols from CIS Exploer. It indicated the selected symbol as RED color and pop window tells that "can not found part information for xxx" as below.

then I compare my configration with my colleagues' , everything is almost the same, except one difference that: When launched in ORCAD, the information in Session Log Window is different. Their's log text contains specific path address“INI File Location:E:\CadenceLib\SPB_DATA\cdssetup\OrCAD_Capture/16.6.0/Capture.ini”， but mine did not (just as the picture shows).

I doubt that my Cadence does not found the INI file under correct path. However, I checked my Environment Variables, my user Variables contains HOME, whose value is "E:\CadenceLib\SPB_DATA", and it is correct. our ini file is stored here. I also check CDSROOT, it's correct too. After copy a new variable "PATH", value" %CDSROOT%\openaccess\bin\win32\opt;%CDSROOT%\tools\capture;%CDSROOT%\tools\pspice;%CDSROOT%\tools\specctra\bin;%CDSROOT%\tools\fet\bin;%CDSROOT%\tools\libutil\bin;%CDSROOT%\tools\bin;%CDSROOT%\tools\pcb\bin;"  still not help.

Could someone save me on this? Nearly MAD.....

Thanks!

Gloss- center between pads not working

October 8, 2018, 8:02 am

≫ Next: NetList Error- SPCODD-47

≪ Previous: Can not place ORCAD sch symbol

$

0

0

I have a 0.8mm pitch BGA that I am trying to center traces between pads. For example I have 4 mil spacing (via to cline) on one side and 3.8 mil spacing on the other side. I've changed the minimum move to .01 and added the layer to glossing subclasses to no avail. It seems to be doing something, but the traces I'm interested in are unaffected. I do not have fixed properties set.

Thanks

Viewlog results:

Line Center Between Pins Stats

Number of Glossing Attempts                   : 1970

Number of Actual Glossings                    : 2

Number of Glossings Aborted by DRC violations : 53

Number of Glossings Aborted by No-Gloss nets  : 0

What am I missing? 

---

NetList Error- SPCODD-47

October 8, 2018, 5:02 pm

≫ Next: Signal names in traces or pins

≪ Previous: Gloss- center between pads not working

$

0

0

Hi,

I am getting the following error while creating the netlist. I tried to go  line no 11 as mentioned in log. However, couldn't find the exact part which is having issue.. Please guide.

Loading... E:\RAHUL\4LCD VER 2.0\ALLEGRO/pstchip.dat

Loading... E:\RAHUL\4LCD VER 2.0\ALLEGRO/pstchip.dat

Loading... E:\RAHUL\4LCD VER 2.0\ALLEGRO/pstxprt.dat
#38 WARNING(SPCODD-38): Terminating character ':' not found on line 11.
ERROR(SPCODD-47): Packaging can not complete because the file E:\RAHUL\4LCD VER 2.0\ALLEGRO/pstxprt.dat could not be loaded. There might be syntax errors in this file. Ensure that the syntax is correct before proceeding.
ERROR(SPCODD-382): Error at line 11 in file E:\RAHUL\4LCD VER 2.0\ALLEGRO/pstxprt.dat. Error loading the parts list file

#9 ERROR(ORCAP-36026): Unable to read logical netlist data.

Signal names in traces or pins

October 11, 2018, 2:21 pm

≫ Next: ODB++ Missing Pads

≪ Previous: NetList Error- SPCODD-47

$

0

0

Hi,

Is there anyway to change fond/size/hi-lite the netname in traces or pins in allegro?

Thanks,

TiBo

ODB++ Missing Pads

October 12, 2018, 10:41 am

≫ Next: DRC

≪ Previous: Signal names in traces or pins

$

0

0

Hi, we are using 17.2. When we use the latest ODB++ V8 to extract files, a couple of our suppliers are saying that there are missing pads on internal layers. When we check using the ODB++ tool, we're not seeing the problem. We also viewed the file with CAM 350 and did not see any missing pads. Anyone else experiencing this? Thanks.

DRC

October 12, 2018, 2:21 pm

≫ Next: 17.20: Unable to check out Capture after applying HotFix 048 - Anyone else with this problem?

≪ Previous: ODB++ Missing Pads

$

0

0

Hi

I have noticed that during DRC in OrCad capture if pins are passive and not connected there are no warnings. Is there a way to check all unconnected pins and single net nodes?

thanks vadim

17.20: Unable to check out Capture after applying HotFix 048 - Anyone else with this problem?

October 15, 2018, 2:25 am

≫ Next: Intertool Communication

≪ Previous: DRC

$

0

0

Having found HotFix 048 in the support area I downloaded it and applied it this morning.

(Previously applied version was 047.)

Invoking Capture results in an error message "Unable to reach the license servers ...etc"

and that I should verify the CDS_LIC_FILE settings (which has not changed).

Invoking Allegro PCB Editor works fine.

Anyone else seen this?