Could anyone suggest 2 layer impedance controlled PCB stack up
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PCB DESIGN
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Changing drill size for a particular component in Orcad PCB Layout
I was wondering how I can increase the drill sizing (drill layer) for a component (Test Point) in Orcad Layout ?
Thanks!
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Impedance calculation in inner layers
I have a 6 layer board where layer 2 and layer 5 are ground and power plane other layers i.e, layer 1,3,4,6 are conducting layers.
While routing on the top layer the impedance is calculated taking the reference of layer 2 as it is a ground layer though Impedance calculation happens based on stack-up and materials used in each layer but for inner layers layer 3 and layer 4 how the impedance will be calculated? which layer will be considered as a reference for impedance calculation ?
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OrCAD Layout Library Manager crashes on SaveAs
I use OrCad 16.2. I have a custom library that I use in Layout. I have often used "Save As" to add a footprint from another library, or board layout (.max file), to my custom library. Suddenly, it refuses to work. I select Save As, modify the footprint name as needed (or leave it un-altered), select my library from the drop-down list, and click OK -> the library manager window disappears. I can select the Library Manager window from the Windows taskbar to bring it back up, but the footprint is not added to my library. Anybody run into this and have a solution?
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change Pin size of block in hierarchy design
Hi,there.
I'm now using hierarchy design. but I found that the pin size displayed in the block is too small that makes it difficult to view. Are there any ways too make it bigger?
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Capture crashes when running DRC
I'm learning to use Capture, and when I get to the point where I need to run DRC, the program starts not responding and crashes. Any ideas?
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Auto Rename Ref Des in 17.2 - space between characters?
I am using the auto rename function, and when I select Preserve Current Prefixes, it adds a space between characters, such as C 147 instead of C147. I've tried changing the settings, but I can't seem to get the ref des without that space. What am I missing? Any help would be greatly appreciated. Thanks.
Alexis
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Rat shown on via despite connection
In Allegro 17.2 HF045 when I add shape or cline to connect a pin to pin still the rats for some via is shown. As in picture below clearly both pin are connected but the rat is shown. How can I fix this? This happen in many part of the board.
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PicknPlace File generated from Orcad Layout is not in correct format
The manufacturer is stating that the pick n place file (XY data file), the locations are not referring to the body center for most of the components. I was wondering how I could make it so that the Pick'n'Place file will correspond to the center of the components ?
Thanks!
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Hide a schematic net name
Hi, I would like to be able to name a net in OrCAD Capture, and then hide it so it doesn't show on the schematic (or, at least in the exported PDF of the schematic). I have previously used PCAD that allowed me to do this simply by ticking a box in the net properties. The net name could then be viewed by hovering over the net.
I found this a useful feature, as it allows me to name nets that are short (maybe only one grid length) on the schematic, but are fairly long or require special constraints on the PCB, but without cluttering the schematic itself.
I'm using 17.2-2016 S043 currently, but would happy go to S046 if it happened to have this feature!
Thanks.
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Renaming caused problems with pin pair definitions
After renumbering and backannotating the ref des on a design, DRC's appeared on BUSS signal lengths since the U* are no longer the same and a few of (but not all) the pin pairs were different since they referenced different U* numbers. Is there any way to avoid this inconvenience? We're using 17.2-2016. Thanks for any guidance you can provide.
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Defining Vias With Different Anti-Pads/Selected Layers In Positive Planes
Engineer has requested a smaller anti-pad on only 2 plane layers for a via on a high speed diff pair. I've created the special via with the different anti-pads on the 2 layers (whose names match the .brd). When I replace the vias in question, the plane clearances still remain at the old diameter. I updated the shapes on the appropriate planes to void to Thermal/anti instead of DRC, and updated the shapes, but I'm still seeing the old larger clearances. I'm using positive planes by the way. What other setting do I need to look at in order to make this smaller anti-pad work? Thanks for any advice you can provide.
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PCB Editor is slow or app stop woking when I trie to move a part or symbol
Hi,
I am having a lot of problems with PCB editor application. Always, when I trie to move a symbol or any part on the canvas it takes a lot of time and some times the application takes a lots of time to respond or chash. Its like the program is very unstable. I reset my computer. I Download the latest drivers for my video card and install the latest hot fix and nothing change. Is impossible to work like this. Attached you can find a video of my screen with an example of the problem. You can use VLC media player to watch the video. The specs of my computer are:
GeForce GTX 1050
Intel(R) Core(TM) i7-7700HQ CPU @2.8GHz
16 GB RAM
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How to delete components using script
I need to delete a bunch of components (like 100 caps), I tried looking around the command to find a component using console commands but not luck.
What's the script equivalent of Find->component
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Not allowing Dynamic shape on etch layer
I have a 4 layer design that I thought looked good but I keep getting DRC errors about all of my pins being to close to GND and/or 5V.
Looking into it my plane shapes are static and all of my pins are connected to both planes.
When I make them Dynamic they move from the Etch Class to the Boundary Class.
If I try to redraw the planes as dynamic on the Etch they automatically appear on the boundary class in the subclass I chose for the etch layer (draw ETCH/POWER and appears as BOUNDARY/POWER).
I can redraw as static and they appear on the right layer but the second I switch it to dynamic it does the same thing.
Any help would be appreciated.
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ERROR in 3D Canvas Viewer Export to STEP File.
Hi,
I am trying to export the STEP file from 3D viewer but it gets exported and i see list of errors/warnings.
Component model 'User_Library-RES_1609-0603.step' not found - ignoring for 'C119'.
Component model 'User_Library-RES_1609-0603.step' not found - ignoring for 'C55'.
Component model 'User_Library-RES_1609-0603.step' not found - ignoring for 'C58'.
Component model 'Microminiature_SMT_Side_Actuated.STEP' not found - ignoring for 'SW2'.
When it gets exported it looks good in A360 Viewer. But the PCB is shown as blank or hollow. Only outline is shown. Why is it like that?
But when its imported into other cad tools. It appears scattered.
What could be the problem?
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Calculation of microstrip impedance in topology extraction (Allegro PCB SI)
I am new to PCB SI. I have got a problem of calculated microstrip impedance in Allegro PCB SI.
I could address the problem that the doubtful calculation results were the microstrips whose traces were tapered trace and manual shape trace
Impedance calculation of tapered trace or multi-width trace seem use only smallest width trace (The result of tapered one and uniform smallest width was always the same)
I understand that characteristic impedance of different trace width is different. To solve this, high resistance with small footprint is added with one pad placed in place of the taper and another pad connected to GND.
Will this method give good approximation??
Impedance calculation of manual shape trace give too different result with usual connection line (same width of rectangular shape vs Cline)
Different width of manual rectangular shape trace was also tried, but calculation result was not absolutely changed.
I have no idea how the calculation input and method were used. Or program PCB SI do not support manual shape trace?
Finally, I found in help menu about RF PCB components model (Allegro RF PCB library reference >> Microstrip component) that include taper, T-junction, etc. What program use those model for calculation?
(My package include only Capture, PCB editor and PCB SI)
Thank you in advance for any response.
Nuttawut
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SigXp -> CM
Hi,
I've imported a single line topology with impedance and PD defined into CM as an ECS.
However nether of these values show up among the constraints.
What is the proper way to transfer constraints from sigxp into CM?
(OrCAD PCB SI)
Thanks
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When using package symbol creator, standard library of footprint no longer showing
Quite often I use the package symbol wizard to create new parts for my design, however recently when I go to select the psm file for the holes I can no longer find the standard examples like PAD70CIR45D. It appears to only show .psm in my Allegro folder which stores custom .dra and .brd files. Any advice on this is greatly appreciated. I have inserted a screenshot of the problem for clarity.
Thanks,
James
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Xtalk simulation
Hi,
Is there a way to extract coupled traces into Sigxp directly in OrCAD PCB Designer Professional or OrCAD PCB SI?
I've set up Geometry Window, Min Coupled Length, Cutoff frq, but the extracted topology is always just a single line one.
Thanks
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