I am using Orcad 17.2. I am getting " Error: Could not connect to library database " when I try to search for a component by clicking on "Place' ->"Pspice Component" -> "Search"
Thank you
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" Error: Could not connect to library database "
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Best way to do blind/buried RF vias?
I have some RF nets routed on internal layers. The layer transitions typically involve a number of micro-vias (i.e. 1-2, 2-3, etc.) and sometimes buried vias. In either case, I often need to clear out antipads on the layers above and below the via capture pads to get rid of extra capacitance. For example, if I'm going from L2->L3 and I have ground plane on L1 and L4 I'd need anti-pads on L1 and L4.
The way I've been doing this is to create, say, a b/b via in the Pad Editor from L2->L3 and then manually adding voids on the PCB on L1 and L4. This is tedious and error-prone, and it's a pain if I have to move that via later. I can create the via in the Pad Editor with the anti-pads (but no Regular Pad) defined on L1 and L4, but then the hole for that via is generated in the L1-4 drill file, not in the L2-3 drill file as it should be.
Can anyone think of a better way to do this?
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Place parts popup doesn't display
When I choose Place -> Components Manually, the popup window that used to show all the parts in the netlist no longer pops up. The only way I can add parts is to drag them from the schematic.
How do I get the popup window back? (It used to show)
I'm using version 17.2-2016.
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HDL Entry - Create Package vs Symbol
Hi,
Please help me on the creation of symbols by HDL entry.
I need to create ONE Symbol associate to ONE Package.
Because in the current design, when generate the Symbols (new symbols). HDL is automatic add this symbols to other packages as picture:
I want to make like:
sym_1 is just only associated to C0402_CAPACITORS_0402-NA-NA-0U1F
sym_2 is just only associated to C0402_CAPACITORS_0402-NA-NA-1UF
When I generate sym_2, HDL will add sym_2 to sym_1 group.
Hope your reply.
Thanks so much,
DongRD
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The value of the $SPLIT_INST_NAME or LOCATION property on instance XXX is not specified
Good afternoon,
while using Allegro Design Entry HDL 17.2 I got the warning shown in the title.
I place a component (LTC6903) and, as far as I can tell, this should not be a split component. However I get the warning and the following detailed message:
"Description : WARNING(SPCOCD-23): The value for the $SPLIT_INST_NAME or LOCATION property on instance: ltc6903, pathval: i14 is not specified.
You must specify a value for the LOCATION property if the SPLIT_INST = TRUE property is present on the instance
or specify a value for the $SPLIT_INST_NAME property on the instance."
Could anyone explain what the message means and how to get rid of it?
Many thanks,
Paolo
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Interval of components
Hello everyone!
Oftenly use the .txt netlist file to import netlist into the board project.
Question: is there any way to discribe an interval of components in a short form? For instance, I have a row of resistors R1, R2, R3, R4, R5.Is it possible to write them down as R1...R5 or R1-R5? (actully, tried both variants, didnt work).
Appreciate the help.
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SDA or System Capture and Simulation
We have now Allegro 17.2 installed, i tried SDA, which looks very promising, but I could not figure out if it already supports simulation, e.g. PSPICE. Anyone? It would be very nice to start test-driving this tool in a simulation environment, before we may go productive with it in a few years.
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Unable to set an image to a hierarchical block
Hello there,
I have been using the trial version of Orcad capture for several weeks and i was able to "Edit Part" of an hierarchical block in order to put an image there.
Now i bougth the license for the suite OrCAD EE Expert with version 17.2.24 and i am not able to do it anymore, is this some kind of bug, anyone is suffering also this?
I have tried by installing and unstalling everything, but nothings seems to work.
Best regards.
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padstack multiple drill problem
Orcad16.6-2015 pastck desinger. I was trying to design a pad with multiple drill and got error/warning as below:
Multiple drill hole array is not contained within all pad boundaries.
Could someone help?
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Ratsnest Display does not work right if Slide Etch is enabled during a "Move or Drag operation" Allegro 17.2 S047 - Allegro 16.5
A few pictures to explain
Symbols with ratsnest on before a move operation "Looks OK"
Next Slide Etch is enabled, R3 is selected and moved "Rats disappear on R3. This is the inverse of Rats on. If rats are on and a component is moved all rats remain on but nets for r3 will become dynamic and move to indicate a good placement location. See Pic below. This is working this way only if "Slide Etch" is enabled.
Changing things around a little. This time Rats are turned off and R3 is moved, Rats show as expected. "Notice Slide Etch is un checked"
Last picture shows a move operation if rats are off and slide etch is enabled. "No rats turn on everything is blank" Expectation is for rats on R3 to turn on.
Something seems wrong with this. Slide Etch enabled is having a negative impact on how the rats are displayed depending on the rats mode either Rats On or Rats off.
Any thoughts ?
Thanks.. Paul.
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New File...Open Dialog Box?
Hey guys...I searched the forum and came up empty. If this has been discussed and answered before, please, be gentle.
I am running v17.2 S048 and have new dialog boxes. The one in particular that gives me trouble is the File..Open dialog. It now no longer seems to be a Win10 dialog box, instead it seems to be an Allegro specific dialog box.
New v17.2 S048 File...Open Dialog
The old dialog box looked like this:
This gives me trouble because many of my designs reside on network servers and are not easy to access anymore. Plus, it just looks wonky and I don't like it!
Is this a simple setting change or is this the new normal?
Tom
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ORCAD-PSPICE: Monte Carlo, Save bias point and load bias point options grayed out for DC sweep....also I can't see CGS and CGD during bias point simulation, only CGSOV and CGDOV.
When watching tutorials, i can see the users click on simulation profile and all the tick boxes are tickable. In my case, some of the tick boxes are grayed out. The image below shows the problem.
Another problem is that when performing bias point analysis, i can't see CGS and CGD, only CGSOV and CGDOV. Again, I have seen in tutorials that both should be visible during bias point analysis.
or maybe the derivatives are the capacitances?
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Stack up Table Zone ordering
With out physical moving the text, is there any way to reorder the below zones starting zone 1 first?
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Highlight specific Via style
Many of our designs have multiple via styles including different sizes and different layer spans.
I am working on a 14-layer design and need to find all the vias that span from L1-6. I have the layer labels turned on and can see all the 1:6 vias, but the problem is that I have hundreds and hundreds of them. I was looking for a way to highlight a specific VIA style, but couldn't come up with a slick way of doing this. I have turned off all layers below L6, but I still have 1:2,1:4, 1:10 and thru vias that stay turned on.
I would love to make these 1:6 vias all bright yellow so I can see them quickly.
Thoughts?
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Coupling capacitance
Is there a way to extract the coupling capacitance between differential pairs in Allegro PCB Designer?
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Ignore component in the netlist
Hi everyone,,
I trying to ignore a component in the netlist but I not have had successful.
I want to have a component in the BOM but I wan't it in the netlist ( for import in allegro).
I tried the SPiceOnly property but in this case I don't have the component in the netlist and also in the bom. I see the BOM_IGNORE property. Is there a same property for PCB footprint (ex. PCB FOOTPRINT_IGNORE or NETLIS_IGNORE) ? How can I solve this problem?
Thanks.
Filippo
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shape min thickness
Hi All,
Is there a way to set the shape minimum thickness?
Thanks.
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Setting Layout constraints in ORCAD Capture schematic
Hi,
Can any one tell me how to navigate through ORCAD capture CIS to set PCB layout constraints which help me saving time...is it possible to set constraints like grouping/class-class spacing,pinpair etc in capture instead of allegro pcb
Your suggestion will be very helpful for everyone
Regards,
Gowtham
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Match Group..... Option in Relative Propagation Delay is disabled
Tried to create a Match group of several differential pairs in Allegro Professional 17.2. The option is however disabled/greyed out for diferential pairs.
Tried the same with single ended signals and here the option was available, Then found that only NET types are possible to match this way.
How is it possible to match several differential pairs, Dpr types, that belongs to the same bus. 16 pairs in number.?
I found that It is possible to expand all the differential pairs (Dpr) and select their individual subnets (Net types) only, one by one, and then create a match group to match their lengths, but this seems a little awkward.
How may I proceed to match the lengths of multiple differential pairs and create a group of DPRs?
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Can't create module in allegro 17.2
Dears,
I finished a small design now and need to create a panel with 10 boards of this same design in one PCB.
I searched for a solution here and it seams that I have to create a module then place it in the panel PCB file.
The problem is I can't find the "Tools > Create Module" command.
My question is where is the create module command located in Allegro 17.2?
Is there another way to create panels?
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