Hi All,
I have Altium PCB file, that i saved in ASCII, as per procedure describe in the Document. When i import this ASCII file in Cadence using CAD translator, the File is imported successfully but without the components. Please help me out, what i am doing wrong?
How can I assign "Show rat->All" in hotkey?
Thanks.
I have a number of dynamic shapes which poured correctly but after checking the Constraints Manager for errors. Some of the pours failed to pour or gave unusual shapes.
Like here where the re is a static pour to illustrate where it should pour and yet the dynamic pour adds a strange curve.
Or here where the outline is shown in light and there should be high voltage clearance to the pads, but the pour has added a joining curve to the pour which was not requested.
This is in Cadence 16.3-053 as we cannot update the design to the latest.
I am looking to see if there is a way to import through the schematic a netlist pcb label.
What I am looking to is is create a symbol in the schematic with a ref designator which represents the PCB part number
that would be put in etch in the pcb.
I know I can create a pcb symbol that has text in it that would be carried over in the netlist but I want to know is there a way to bring over the symbol with the
pcb number for that actual board so I do not have to edit the text everytime in the pcb layout.
Is there a way to put the pcb part number in a property of the schematic, like a resistor or capacitor value, which comes across in the netlist.
Hi forum. I think I must be missing something.
When I try to export OBD++ files, the non-plated drill hits seem to be missing. I'm using 17.2-2016 S050
Here are my settings:
page 1)
Page 2)
Page 3)
Page 4)
And the resulting artwork, the blue circles note where the NP drills should be.
In my CAM tool, I've inspected the drill table, there is no tool code for the drill size I'm looking for. It's like the drill is being completely omitted.
Any ideas would be helpful.
Thanks.
In this circuit an error is displayed. What may be the reason(s)? 
The error message is '
'
I'm not sure about this, hence asking.
I usually check silkscreen by visually looking at the board on the screen.
This method has failed me now that the boards are getting larger, besides silkscreen being on so many different classes.
Is there a DRC that can be set to check for overlapping silkscreen? (without using autosilk)
Thanks!
Hello,
Excuse my question, I am new to PCB Design.
Is the Cadence SPB / OrCAD 17.2 release one that includes BOTH OrCAD and Allegro of Cadence PCB software ?
I want to use Allegro not ORCAD.
I would like to purchase Allegro but I only see this Cadence/OrCAD 17.2 SPB release on the Cadence website.
Can someone let me know - if I purchase this SPB release do I get BOTH OrCAD and Allegro ?
Thank you.
Anyone having 4 layer .brd file with diffencial pair and usb lines and ethernet lines routing sample board please share me my email id: chaitra.9007@gmail.com, I am new of rf design, I want to learn so please share me
Hey all,
I've been tasked with replacing a 30 pin connector on our boards, with a new one after the old one was declared obsolete. I've updated the schematic by altering the old connector and saving/update/replace cache. When I try to create the netlist to bring the changes to pcd editor, I am met with an error.
ORCAP-32007 or ORCAP-32006
I am completely new to PCB design, so I may have made a fatal error early on that's preventing me from doing this?
Is there an easy way to replace components? I'd like to keep all of the same connections to the same pins, and just replace the symbol/footprint.
INFO(ORCAP-32005): *** Done *** Spawning... "C:\Cadence\SPB_17.2\tools\bin\pstswp.exe" -pst -d "C:\USERS\DARCY\DESKTOP\ORCAD TRAINING\TRAINING\TCC\TCC_0458-0000_REV2_SCH_14-12-02C.DSN" -n "C:\USERS\DARCY\DESKTOP\ORCAD TRAINING\TRAINING\TCC\allegro" -c "C:\Cadence\SPB_17.2\tools/capture/allegro.cfg" -v 3 -l 31 -s "" -j "PCB Footprint" -hpath "HPathForCollision" -lite Loading... C:\USERS\DARCY\DESKTOP\ORCAD TRAINING\TRAINING\TCC\allegro/pstchip.dat Loading... C:\USERS\DARCY\DESKTOP\ORCAD TRAINING\TRAINING\TCC\allegro/pstchip.dat Loading... C:\USERS\DARCY\DESKTOP\ORCAD TRAINING\TRAINING\TCC\allegro/pstxprt.dat Loading... C:\USERS\DARCY\DESKTOP\ORCAD TRAINING\TRAINING\TCC\allegro/pstxnet.dat Exiting... "C:\Cadence\SPB_17.2\tools\bin\pstswp.exe" -pst -d "C:\USERS\DARCY\DESKTOP\ORCAD TRAINING\TRAINING\TCC\TCC_0458-0000_REV2_SCH_14-12-02C.DSN" -n "C:\USERS\DARCY\DESKTOP\ORCAD TRAINING\TRAINING\TCC\allegro" -c "C:\Cadence\SPB_17.2\tools/capture/allegro.cfg" -v 3 -l 31 -s "" -j "PCB Footprint" -hpath "HPathForCollision" -lite
netrev run on Jan 29 16:13:17 2019
cpu time 0:01:05
Ripup etch: No CmdLine: netrev.exe -y 1 -z -i C:\USERS\DARCY\DESKTOP\ORCAD TRAINING\TRAINING\TCC\allegro C:\Users\DARCY\Desktop\Orcad Training\training\TCC\pcb_0458-0000B.brd C:\USERS\DARCY\DESKTOP\ORCAD TRAINING\TRAINING\TCC\allegro\TCC2019.brd ------ Preparing to read pst files ------ Starting to read C:/USERS/DARCY/DESKTOP/ORCAD TRAINING/TRAINING/TCC/allegro/pstchip.dat ------ Oversights/Warnings/Errors ------
WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. WARNING(SPMHNI-363): Signal model '33OHMRESISTOR1_16W5_0402_SM_735_33' not found; may effect xnets and electrical constraints. #1 WARNING(SPMHNI-192): Device/Symbol check warning detected. [help] WARNING(SPMHNI-194): Symbol '30PINCONNECTOR' used by RefDes J12 for device '30 PIN CONNECTOR_0_30PINCONNECT' not found in PSMPATH or must be "dbdoctor"ed. ------ Library Paths ------ PSMPATH = . PADPATH = .
COMPILE 'logic' No error detected cpu time 0:01:05 INFO(ORCAP-32005): *** Done *** |
I'm curious if there is a standard report in Allegro that summarizes the total component area of a PCB design? I would think it would be based on the Place Bound layers. I don't seem to be able to find anything obvious in the standard reports list.
Hi,
I'm using OrCAD pcb Designer professional version 17.2-2016 with Hotfix_SPB17.20.049. I tried to tune some traces to match them (data and control signals for a emmc, and I have already set the match group in constraint manager).
But it seems I can only tune traces on the top and bottom layers, not inner layers (I changed the options to inner signal after choose route->Delay tune. ) I'm wondering why I can not tune traces on the inner signal layers. Did I miss any setting, or is it a bug for version 17.2-2016?
By the way, I read that allegro 16.6 has Auto-interactive delay tune, but I did not find this option in pcb Designer professional version 17.2-2016, why?
Anybody knows about this, any reply is appreciate. Thank you in advance!
With best wishes
Mingyuexin
I have completed the PCB design, However as can be seen in attached file <padstack marker in PCB editer>, there are the markers and same are appearing in gerber output (attached). Please suggest
what is the error and how to remove this ?
Regards.
Hello,
In Sigrity OptimizePI (17.2 Linux) tool, the what-if analysis simulation fails and gives this error message "Error occurred while doing what-if analysis based on shorted decaps."
Could anyone tell me where to search in workspace to find out where is the shorted decap ?
Thanks in advance.
Hi,
I'm trying to view and manipulate the design of an evaluation PCB for the MAX2870 Phase-Locked Loop chip. Maxim have made a .pcb and .sch file available on their website (under "Tools & Models") but I couldn't open either with any software I'm familiar with (Kicad and Eagle).
After emailing the company to query what software to use I got this reply:
The schematics and the PCB files available online can be opened by the Orcad - cadance which is the industrial standard for sharing such files. A free version of the said software should be available online.
So I downloaded the OrCAD Lite package (version 17.2) and installed it. Using the "Capture CIS Lite" software I do have an option to open .sch files, but upon trying to open the MAX2870EVKIT-schematic.sch I get the following message:
Has anyone come across this problem before, or have any recommendations so that I can access the file?
Thanks in advance,
Matt
WHEN LICENSE IS IN USE ANS I AM USING THE SOFTWARE FOR PCB DESIGN THE LICENSE ABRUPTLY FAILS, SUDDENLY I WILL GET LICENSE FAILED ERROR. HERE IS THE DEBUG.LOG data
16:49:49 (cdslmd) Wrong hostid on SERVER line for license file:
16:49:49 (cdslmd) C:\Cadence\LicenseManager\license.dat
16:49:49 (cdslmd) SERVER line says FLEXID=9-7ECFA92B, hostid is FLEXID=9-7ecfa92b
16:49:49 (cdslmd) Invalid hostid on SERVER line
16:49:49 (cdslmd) Disabling 3 licenses from feature OrCAD_Capture_CIS_option(AEB86839E90E8FFF4F80)
16:49:49 (cdslmd) Disabling 3 licenses from feature OrCAD_PCB_Designer(BEB8A859FE33F7B7D6DF)
16:49:49 (cdslmd) Disabling 3 licenses from feature OrCAD_PCB_Editor(6EE8084943CDE8FA7D1F)
16:49:49 (cdslmd) Disabling 3 licenses from feature OrCAD_PCB_Router(1E8848796A0CA15F0CC3)
16:51:49 (cdslmd) No valid hostids, exiting
16:51:49 (cdslmd) EXITING DUE TO SIGNAL 25 Exit reason 2
TRIED CHANGING THE FLEXID TO ALL SMALL LETTERS BUT GOT ANOTHER ERROR STATING INVALID LICENSE.
PLEASE SUGGEST HOW TO RESOLVE
REGARDS,
JESH
I'm having problems with Allegro Viewer 17.2 on Windows 10 Enterprise and was wondering if this are known issues.
1) If I don't run Allegro Viewer as Adminstrator then report windows don't work. What I mean by this is report window opens (like Show Element or Measure), but the body says "Can't reach this page, make sure the web address is correct, search for this site on Bing, Refresh this page." If I run the viewer as Adminstrator than the reports display correctly.
I completed wipe everything Cadence from my machine (uninstalled, wipe all cadence & allegro files, removed all cadence and allegro entries in the registry, rebooted, fresh download file from Cadence, and reinstalled). I tried installing both as user and administrator with the same results.
2) I can't save display settings. When I use the menu command View -> UI Settings -> Save Settings nothing happens. Looking at the .JRL log file it says "Command not found: save_settings"
After just upgrading everyting to V17 I noticed that the File->Export->PDF is not functional in OrCAD Pro. Is this a special license that I missed? It's the only menu tree item that does not work for me.
Hi!
Could someone please shed some lights on Schematic Nets vs Flat Nets?
Thank you.
Well after years in 16.x release with its 3D, I finally plunged into 17.2 S051 and the new 3D canvas tool is "broken". How does one rotate and tilt like the old 3D tool? I can not find any instructions that related to tilt and rotate. Pan and zoom only work. I used to be integrated into the mouse center button in the old tool.
Anyone have some pro tips for an old pro?