how can i purge all unused symbols completely?
i deleted all unused symbols but they are still showing on the netlists.
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purging used symbols but still showing on the netlist
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[OrCAD PCB] Undo history constantly disappears
Hello
While working on our PCB designs, the undo history constantly clears out and we cannot undo changes recently made.
community.cadence.com/.../2019_2D00_04_2D00_25-13_2D00_33_2D00_01.mp4
It seems like every other command triggers this erasure, rendering the undo / redo functionality practically useless.
Is this a feature or bug?
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How many Vias can be placed in the same location?
I am attempting to place microvias and buried vias on the same XY locations. As these will be constructed at different times in the manufacturing process. But The vias do not appear to connect properly.
Can anyone suggest if this is possible?
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board geometry
Using 17.2
I created my board outline using class/subclass 'Board Geometry/Outline'. When i create artwork is tells me that the preferred sub class is 'Design_Outline'. How do i change the subclass? If i select the outline, and use change class/subclass, 'Design_Outline' is not listed. Both 'design_outline' and 'outline' appear in the color dialog under 'Geometry'
Thanks
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offsetting a void shape
hello
how can i offset a void shape?
for instance, i want to make a 40um square shaped void a 30um square shaped void.
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How do I export a BOM to a custom Excel template file using the OrCAD CIS function Reports-CIS Bill of Materials-standard or Rrystal Reports?
我想为BOM创建Excel模板，使用OrCAD的报告 - > CIS物料清单 - >标准或Rrystal报告将项目的bom导出到此Excel模板。我该怎么做呢？我使用OrCAD的报告 - > CIS物料清单 - >标准来导出Excel，如下所示。
What do I need to do to specify output to my custom Excel template?
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17.2: Non Plated holes disappearing in odb++ data
Hi,
Is there a special reason why odb++ output deletes non plated holes which contains no regular pad, thermal pad and anti pad? The padstack only contains the drill size + symbol and all the pad info is None.
I discovered this error after I got feedback from the manufacturer. Apparently the drill showed up in the gerber and NC drill output, but not on the odb++ output data. They used odb++ data and not the gerber data. The strange thing is that the drill table, in the odb++ data, showed the non plated drills with the character 'k' I defined, but weren't present on the location I placed them.
After adding a thermal and anti pad to the padstack, odb++ didn't delete the drills. I'm only using positive planes, so why should I even use thermal and anti pad?
They software version I use: OrCAD PCB Designer Professional 17.2-2016 S051
Regards,
Michiel
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Changing field values in Simulation profile using TCL
Hi,
I am using Allegro Design Entry CIS v 17.2. Here, I want to change the field values of the sim profile(eg: Run time, RELTOL, Probe window fields) using TCL script loaded at command window. I know that the information of the sim profile will be stored in .xml file at CAPTURELOG. I would like to know is there a way to link this information in the .xml file to edit the sim profile fields using TCL commands. If not, how to change the fields directly using a TCL command.
The idea here is to change the values without manually entering them.
Can anyone please help me out in this? It would be great if I could get some reference material for better understanding.
Regards,
Yashmitha
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Need some advice on how to complete this one microprocessor connection.
Hey all,
I've been posting here for a few months now, and would not have gotten as far as I had without the community here. I am just about ready to send the board off for prototype when I noticed I have a rats nest on one on the FPGA pins. This wasn't on the original board design, and I didn't go anywhere near this part of the board when making my edits.
My question is, what are my options here? It will not let me simply make a trace to the two points. This is a top-bottom rats nest as well if that helps.
When I select Display/Show Rats/Nets, the highlighted parts appear identical, and the connections on the original board file appear the same as the new (at least in the area that I'm seeing the rats nest.).
Stumped...
Orcad Top
Real World Top
Real World Bottom
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How to customized propertes of Edit->Browse->Part in ORCAD
Hi,
I want to add PCB Footprint in this windows view. It's very useful to check the PCB footprint of all parts in schematics. But I couldn't add PCB Footprint column in this widows.
Peter
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Unable to Route gridless in 17.2
I have basic grids set as 0.1mm in a 17.2 design, but need some routes on a different grid. When I select gridless routing, the rout still snaps to the grid!
How do I route gridless when selecting gridless refuses to work. (The routes needed are on a 15thou trace with 15thou spacings for a flexi!)
But the design is a metric system design, with only a small area requiring imperial spacings.
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how to make Pspice model with *.sin or *.spi?
Hello
I writte because I have a problem.
I need incorporate a part on design and fabricant give my file with exteccion *.sin or *.spi. I need *.Lib
can you help my with explication of procedure?
thanks
Leo
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ComponentDefinitionProps documentation
Hello,
I was looking for a piece of documentation about the fields that fall under ComponentDefinitionProps but wasn't able to find any. I had some problems the CLASS field at some point and I am wondering what are the valid values for this field. However, the question is generic and applies to all the predefined fields under ComponentDefinitionProps.
Regards,
Catalin
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Missing AUTO_RENAME Property ALLEGRO 17.2
I'm attempting to rename a selected set of components prior to back annotation. I can't manage to add the required AUTO_RENAME property to the components to do so. Based on the help file my understanding is that there should be an AUTO_RENAME property in the drop down.
I attempted to pass this property in from the schematic with no success.
Result of attempting to rename selected components without the property: "No components wth AUTO RENAME property found on subclass TOP and BOTTOM."
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Pspice -> Edit Pspice Model -> read only?
Hello everybody,
I want to change transistor's beta value(BF), but i can't, because it is set to 'read only'.
how can i edit that value?
Any help appreciated.
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HOW TO REMOVE DUPLICATE DRILL LEGENDS
PLEASE HELP ME REMOVE THIS TOP TO TOP DRILL CHART.
everytime i produce drill legends this top to top overlaps in my top to bottom charts.
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Pin Discrepancies between OrCAD Capture and Allegro Pins on Translated OrCAD Layout PCB File
I am working on a design which was originally done in OrCAD Layout (.max file). I installed the translation utility and migrated it to Allegro. (Currently running 17.2) I have several connectors with mechanical (non-connect) mounting pins defined in the footprint, plus a BGA that has two fiducials in the footprint. For each of those parts, I get the following message in netrev.lst:
#2 WARNING(SPMHNI-184): Device library warning detected.
WARNING: J9 component device pin number mismatch; cannot replace.
The only way I have found to work around this is to redefine the mechanical pins as connect pins and then add them to the schematic symbol. This goes against our normal schematic symbol processes since non-connect mounting pins, fiducials, etc., are not supposed to appear in the schematic. (As differentiated from, say, the mounting holes for a D-sub connector where these would typically be connected to chassis ground for shielding purposes)
Does anyone have a bright idea how to fix this between the Allegro footprints and OrCAD schematic symbols?
Thanks!
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Opening Capture CIS in the background
Hi everyone,
Is there any way can I open Capture CIS in the background in either windows or linux shell? Adding a wire and saving the project from the shell without having to open GUI?
I am new to this, any idea will help
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Cannot add dummy net on No Connection pin
Hi,
I need to put Dummy net on NC pin of a LED. But when i put Dummy net and try to assign to that pin it is showing "cannot assign dummy net to that pin".
I need to put dummy net on that pin for heat dissipation.
Thanks & Regards,
K.Dinesh
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How to run the autorouter in Allegro 17.2?
When I attempt to autoroute, I get no routes done.
Is there a special set-up I need to go through to get the Autorouter to work?
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