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Hierarchical Block Design

May 24, 2019, 1:43 pm
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Hello,

I have 5 questions regarding hierarchical blocks I am trying to make for my engineering team:

1) How can I make my hierarchical blocks that I have created automatically have the attribute “subdesign_suffix”? My goal is for my team and I to use these hierarchical blocks with the maximum ease as possible, and having this automatically is one less step for them to do.

2) When the subdesign_suffix displays in the Cadence schematic, it is automatically populated to the top right of my hierarchical blocks, kind of far away, and I would like to bring it closer to my blocks, and more centered by default. How can I go about doing this?

3) One of my component libraries includes a few components that I do not want - I want them removed. How can I remove these unwanted components?

4) How can I make the library of components that I have created exportable for others to download and use for their future inquiries?

5) Do hierarchical blocks inside of hierarchical blocks work? How does the naming of these components work with respect to their subdesign suffixes?

Thank you!

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OrCAD Tool Bar

May 26, 2019, 10:42 pm
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Is it possible to save the toolbar settings in Orcad Capture CIS 17.2? 

If it's possible where it will be saved and what would be the file name?

Thanks in Advance!!

Dhaya

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CIS Explorer

May 26, 2019, 10:53 pm
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Is it possible to open CIS Explorer with "Query" Tab instead of "Explore", as the default whenever we are launching it.

Dhaya.

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Edit/delete only last segment of trace

May 27, 2019, 5:43 am
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Hi,

I sometimes start routing a part of my board and I always need to change/edit/delete the whole trace.

Is there a way to switch between "whole trace" and "last segment of trace"?

Sometimes its very annoying when I have to redo all routing for a long trace again when I only want to edit the last few segments.

Thank you very much!

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3440 x 1440 Resolution monitor not work well with allegro

May 27, 2019, 7:35 pm
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I'm using 17.2 S54, the allegro with Cadence Help, Stackup.... is scale very small, can't not read the text, Please help

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Copy BB via padstack in Editor. Can't change options settings

May 28, 2019, 2:18 pm
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I get to use this feature extensively for one board.  A year later, have to remember these tricks again when the next MCM substrate comes.

For the life of me, I don't remember how to change Qty, Spacing, and Order.  They're grayed out.

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Block Designing

May 29, 2019, 2:00 pm
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My goal for my current project is to create a Hierarchical Block Library in Cadence for my team and I to use in the future. With that said, here are my questions:

 

 

1) After I have created my hierarchical blocks, how can I export them as a library for my coworkers to import and use in the easiest way possible?

 

2) I would like to use hierarchical blocks inside of hierarchical blocks, is it possible? How does the naming of the larger block propagate to that of the block inside of it? Could you provide instructions on how to use the blocks inside of a block?

 

3) Can we have different versions of a block? My goal is to have a single block with multiple versions of the same said component that would have different configurations.

4) In the component library that I have created, I have extra components in the Component View that I do not want. How can I delete them? (control + delete does not work)

 

 

Thank you for the help, it is very much appreciated.

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Does ORCAD support user-define hotkey?

May 29, 2019, 8:14 pm
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Hi there,

As I know, Allegro allow user to define their own hotkeys according to their own habits.  Does ORCAD support user-define hotkey when design schematics, and how to set up it ?

The orcad version is 16.6. Thanks!

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pdv.exe has stopped working in Allegro Part Developer

May 29, 2019, 8:57 pm
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Hi,

When I take Allegro part developer for symbol editing, I get the following error, Please help me to get a solution for this.

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Can I preserve part pin connectivity when using replace cache or link database part in part manager?

May 30, 2019, 1:27 am
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Hello everyone,

I am trying to change part schematic symbol for a diode. However, I see that after by using either replace cache to another schematic symbol or link database part to which has a different "schematic part" value, the diode's pin connectivity will change. For example, anode is connected to net1 and cathode is connected to net2 previously, after replace cache, anode is connected to net2 and cathode is connected to net1...

I go through my library, found these two symbols just have different orientation, while both pin1 is anode, pin2 is cathode. I think this is the root cause of diode connectivity change. So is there anyway for me to preserve component pin connectivity after replace cache or link database part to a different schematic symbol?

Thank you and have a nice day!

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Bend Line error

May 30, 2019, 5:38 am
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Hi, 
after drawing a board outline and creating zones with specific stack up assigned to them, I wanted to draw a bend line. 
In Create Bend Area window, I set bend line start coordiantes by clicking the canvas. After that I want to set bend line end coordiantes by clicking the canvas again but nothing happens. If I type in the end coordinates manually, I get an error "Invalid bend line end points." What could be the issue here?

I'm using this SW for testing purposes only, hence I use PCB Designer Lite version.

Thanks a lot

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OrCAD capture: Unable to link to database which is hindering the entire process of creating netlist and importing netlist to PCB editor and doing layout.

May 30, 2019, 6:56 am
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Hi,

I am having trouble linking a part to the database. When I try to link, all the other parts in my schematic get approved, but this one temporary part I created says "Temporary: Not approved", and gives me the error "Update part- Occurence..." and says that the database properties do not match my schematic properties. I even tried clicking "yes' for this to update the info. to my database properties, but nothing changes whether I click "yes" or 'no". 

I also tried placing the part again from the beginning but now it says "ERROR(ORCIS-6184): The selected component cannot be placed on the schematic. Refer to Session Log to resolve the error". Any idea why this could be happening? FYI this part is a homemade component and its been added in our database along with footprint and everything else that's required.

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Signal/Power Integrity Problem

May 30, 2019, 9:11 pm
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hi everybody,

i have a problem. i am using the SPEED2000 to extract the netlist from .brd file to run SI simulation.I have checked the error and warning into PCB Board and tool showed a note that: 

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

OUTPUT                                                                                                                                                                                                                 /

WARNING [Via Placement]: Via3420::GND at (117.531mm, 19.191mm) with lower node on Signal$S3 has a placement warning                     /
WARNING [Via Placement]: Via3432::GND at (89.419mm, 19.186mm) with lower node on Signal$S3 has a placement warning                       /
WARNING [Via Placement]: Via3436::GND at (82.014mm, 19.186mm) with lower node on Signal$S3 has a placement warning                       /
WARNING [Via Placement]: Via4394::GND at (12.615mm, 10.387mm) with lower node on Signal$BOTTOM has a placement warning            /

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

This is called "Node Check"

I want to ask that how to fix this node check and disappear them from the board?

This problem points a bit on the simulation field. Hope everybody help please.

Thanks so much!

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Local Library Creation

May 30, 2019, 4:40 pm
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Hello,

I have a couple of questions:

1)    How can I create a local library in Cadence? Can you please send instructions on how to accomplish this?

2)    Once I have created said local library, how can I export this to other people in my group?


Thank you for your time

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Drill Chart versus Drill Figures

May 31, 2019, 1:18 pm
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I have a board and for my fabrication drawing I want my drill chart on one page and my board outline with drill figures on a second page.  The second page is simple, I just use the MANUFACTURING/NCDRILL_FIGURE and these show up on the board outline.

On the page with the Drill Chart, I get the chart, with the figures down the left side of the chart, but I also get all of the figures in the location they are on the board.  This is by including the MANUFACTURING/NCLEGEND-x-y layer on that page.  Is there a way to just get the chart?

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Trimming off one corner of a package outline (Assembly_Top and silkscreen) to indicate pin one.

May 31, 2019, 7:15 pm
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Attempted Actions (OrCAD 17.2, hotfix 55):

RMB->Application Mode->Shape Edit

Option Menu

      Active class and subclass 'Package Geometry'/Assembly_Top

     Vertex Command->Click: select 'Chamfer/Round'

     Corners: tick Chamfer radio button

     Trim(T) set to 10mil

Left click on silkscreen rectangle vertex near pin 1 (6-pin SOT Filled or unfilled, not Fixed):

Problem:There isn't a 'Trim Vertex' option. The only Shape Edit mode menu option is 'Trim Corners', which trims multiple corners.

The part can be freely edited in General Edit Mode

Thanks in advance.

-Keith

Thanks in advance for your help.

    

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WARNING(ORCAP-40202): Pin '2' of comp 'R478' has PINUSE value other than UNSPEC.

June 1, 2019, 2:06 am
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while extracting topology of PL_DDR4_A0, the error as subject occured.

but when i try to set pintype of R478.2 to UNSPEC, well, there is no such a thing as UNSPEC.

possible types are:

Bidirectional  Input  Output OpenCollector OpenEmitter Passive 3-state Power.

what should i do?

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How to get the maximum trace length in our PCB?

June 3, 2019, 5:33 am
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Hi There,

After the layout is done, is it possible if I want to see the longest length of Trace in the PCB? 

please Let me know if is there a way which can show the length of all traces in tabular form or in any format?

Thanks! 

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Undefined Flash symbols

June 3, 2019, 6:44 am
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I am trying to create gerbers for my design.

I keep recieving and undefined flash symbol error message and cannot create the gerbers.

In my aperture list I see the flash symbol that the tool says is undefined.

If I try to refresh my shapes and flash symbols to see if this corrects the problem the flash symbol name is not listed even though it shows up in the actual aperture list.

How can I get the flash symbol listed under shapes and flash symbols under the place menu?

Online I see a flash_convert command to try.

How do i run this command, I use Allegro Pcb editor version 17.2

Thanks

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Flash symbol in Update shapes and flash symbols

June 3, 2019, 8:15 am
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How do I get one of my flash symbols to show up in the Update shapes and flash symbols list.

I cannot create my gerbers due to an undefined aperture.

The undefined aperture is a flash symbol which I have in my symbols directory (.fsm)

If I try to update shapes and flash symbols from within the place menu of Allegro Pcb editor, I do not see the .fsm file I need to try and refresh.

Thanks

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