How to show the PCB designators on Silkscreen?

June 4, 2019, 5:17 am

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Hey There,

I am doing my 1st PCB entirely !

I have confusions here regarding the ref. des. of components and How to show them on PCB.

-When I place the component on my PCB design, the Ref des. comes along with it. but that is in Ref. des. --> Assembly Top (class subclass), that doesn't show anything on PCB I guess when It comes in physical form. Also, I can't see them in 3D model view either in Assembly Top or Silkscreen Top layer when all layers are off.

-Also, when I add the text with ref des. written in it and put it in Manufacturer--> Autosilk_top (class subclass) layer, then it shows in silkscreen layer. but not in 3D model view. it will take me too long to add all ref des manually by text and then add it to the Autosilk_top one by one. 

What should I do here ?? any simple way to do this? I just want to show up the designators on the top. !

additionally, please let me know the difference between --> Autosilk_top, Assembly_top and Silkscreen_top in PCB (as well in ORCAD) :) 

Thanks in advance!

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Packaging Error

June 4, 2019, 9:45 am

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Hello,

I am getting the error "#1   ERROR(SPCOPK-1053): Cannot find a ppt part that matches the instance properties" when packaging my hierarchical reuse block design after I import my hierarchical block designs from another project. My goal is to use my hierarchical reuse blocks in my current project. I am aware that this library of mine shares components with other libraries, which is what I want. With that said, how can I get rid of this error?

Thank you for your time!

Iterated Blocks?

June 4, 2019, 10:11 am

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I have a couple hundred lines, each of which needs its own 3rd order elliptic analog filter. I'm trying to figure out an easy way to instantiate the filters.

I tried using the SIZE parameter on each element of the filter using a bus connecting each, but when I save I get a netlisting error and can't package. I tried to iterate the names modifying the PATH property, but the backannotation gives me errors when I do that. I've attempted to use blocks, but I have the same issues (or it takes a very long time to package).

Any ideas?

Capture 17.2 S051 automatically assigns xnets

June 4, 2019, 10:17 am

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Hi All, It appears that Capture 17.2 S051 is automatically assigning xnets to existing schematic. I think this coincides with the introduction of Constraint Manager for Capture. I’m curious if anyone else has recognized this? It can wreak havoc on net-classes already defined in Allegro.  Thanks. 

creating layer views in artwork control form

June 4, 2019, 2:07 pm

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For what feels like 100 years I've been creating drawings, temporary views, dxf exports, etc. using the artwork control form. I've always exported gerbers manually and never had any issues. We want to transition to ODB++ (I know, late to the party). Anyway, I don't want my drawings or other junk included in the ODB++ export so they can't be in the control form as a film. I am aware of color views, but I don't like the idea of dragging around a bunch of text files with my .brd. There has to be a better way. If not Cadence needs to fix it. 

what should i do to simulate ddr4 sodimm? is there any ibis model for both the sodimm socket and the ddr4 module?

June 4, 2019, 8:00 pm

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as topic.

Import Scaled dxf draw

June 5, 2019, 8:31 am

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Hi

I get a dxf draw file that not 1:1 scale , can I change it in Allegro designer to 1:1 scale?

I'm using 16.6 version

Thanks

Via Stitching and via shielding - in Version 17.2.

June 6, 2019, 5:39 am

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Hello,

I am not able to see Via array option in 17.2  Orcad version. in such case what can we do or what is the method to do the Vias. ?
Additionally, I have 2 layer PCB.. having only ADC, GROUND, 5V and another signal. So what would be the best solution to provide the shielding and stitching to ADC signals.? any suggestions?

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Manipulate place_txt File

June 6, 2019, 7:38 am

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Hey guys,

I have a design with 3000+ parts that I have to recreate. I have a file with XY location and rotation data for in a text file. I would like to be able to do a File--Import, Placement on. I noticed that the formatting of the place_txt.txt file is pretty specific and is ! delimited. Are there any utilities or clever ways to manipulate the XY text file I have to fit the format of the place_txt.txt file?

I would like to open the original placement file in Excel, organize/rearrange the fields to get them in the proper order and then export out a file that I can then import into Allegro.

place_txt.txt file

Board simulation in OrCAD Capture / Allegro Design Entry CIS

June 6, 2019, 2:09 pm

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I'm using OrCAD Capture / Allegro Design Entry CIS under Windows.  When I try to perform a "Board Simulation,"  I get the following error:

****************************************************************************************
ERROR(ORCAP-13082): Failed to invoke "ncvlog -cdslib c:\orcad_projects\demos\Indesign\cds.lib -hdlvar c:\orcad_projects\demos\Indesign\hdl.var -Append_log -logfile c:\orcad_projects\demos\Indesign\Detail.log -message c:\orcad_projects\demos\Indesign\TESTSWITCH.v" as a child process.
::The system cannot find the file specified.
ERROR(ORCAP-13061): 
Process cancelled by user or Errors/Warnings encountered.

From what I gather, ncvlog comes from Incisive, which would appear to be a Linux only product [1]. So, I'm confused - why does the Windows only tool depend on a Linux only tool?  or is there some other license that is needed for ncvlog and/or SimVision for Windows?  I'm part of the Cadence academic program, so I have a pretty complete license for Cadence Allegro & Virtuoso tools.

[1] https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/support/supported-platforms-matrix.pdf

Display Parasitics (missing)

June 7, 2019, 9:19 am

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Hi

I've been Allegro Performance (L) for the longest time and recently switched to OrCAD Pro.  The Display Parasitics feature is missing.  Is this correct? I thought OrCAD Pro and Allegro L were supposed to have the same feature set.

Or has this gotten hidden into some other place?

Thanks

RW

backannotation hang

June 10, 2019, 4:31 am

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https://github.com/chaujohnthan/zcu104hw/blob/master/HW-Z1-ZCU106_Revision_1_0.zip

orcad generate netlist, then import logic from allegro. after that, tools/back annotate... from orcad 

will hang. 

do not know what the matter is.

flex circuit bend line error in 3D canvas

June 11, 2019, 5:42 pm

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Can you have a bend line on a radius show up in the 3D editor? This doesn't seem to work. Any suggestions? Flex circuit needs to bend on radius. Also flex circuit is complex. Any limits on Flex design_outline?

To find unconnected components in Design Entry HDL

June 11, 2019, 8:54 pm

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Hi, 

How to find the unconnected components in Design Entry HDL?

When the schematic diagram is opened in 17.2 HF055 capture, probability cannot be selected by clicking

June 12, 2019, 5:38 am

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After opening the schematic diagram in the capture, the probability can only click on the selected electrical node, not anything, but the area selection is no problem.

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accuracy of power integrity analysis

June 12, 2019, 7:50 pm

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from pdn analysis, select certain dc net, assign sink & source in components & ports, 

then i can perform analysis.

but i suspect the accuracy of the result. if i can not get ibis model of these VRM which are

complicated then pq_vrm, then the usefulness is in doubt.

i can not get any ibis file of the following:

 MAX8902B

MAX15303

MAX15301

TPS51200DRCT

MAX15027

MAX8869EUE18

MAX20751EKX

MAX8556

MAX16052

any suggestions?

Copy Environment to Another PC

June 15, 2019, 12:20 pm

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I have an OrCAD PCB Editor installation (I guess this kind of applies to my Capture installation too) that I've spent years getting how I want it.  Now I want to setup this same environment on another PC.  Problem is, there's no way I'll remember all of the little tweaks I've done over the years to make the installation mine.  Is there a file or set of files that I can copy from the old installation to the new one in order to make them the same?  I'm thinking UI tweaks, padstack locations, footprint libraries, DRC settings, etc.  Maybe some of it is design dependent, and that's fine if that's the answer too.  Thanks in advance for any tips.

STEP File is Blank

June 17, 2019, 2:44 pm

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I am trying to assign a particular STEP file to a footprint in the STEP Mapping tool.  When I do, it shows as blank.  I note that the STEP file is significantly larger than most, but I don't know if that is affecting my issue.  I've got many other STEP files that I've downloaded from various sources, but only this one gives me trouble.  OrCAD v17.2-2016 S055.  Thoughts?

Note: I saw here that someone tried changing the design units, but that didn't help me.

Amphenol ICC 10061122-411420HLF

Simulating circuit on PSPICE Convergence error

June 18, 2019, 7:29 pm

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I'm trying to simulate an one bit ADC using only mosfet transistors but keeps giving me an convergence error

The model info for each of the transistors are 

.model MbreakP PMOS LEVEL 3
+ TOX = 9E-9 COX = 3.8E-15 GAMMA = 0
+ LAMBDA = 0.1 CGDO = 500E-12 CGSO = 500E-12
+ VTO =-0.8 KP=68E-6 COX=3.8E-15

.model MbreakN NMOS LEVEL = 3
+ TOX = 9E-9 COX = 3.8E-15 GAMMA = 0
+ LAMBDA = 0.1 CGDO = 500E-12 CGSO = 500E-12
+ VTO =0.7 KP=190E-6 COX=3.8E-15

Here are the screenshot of the PSPICE error and the design circuit

drive.google.com/open

Can anyone pinpoint what exactly is wrong here? Thank you

STEP Export including STEP Parts and Non-STEP Parts

June 19, 2019, 1:46 pm

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I'm venturing into exporting STEP files from PCB Editor.  Things seem to be going fairly well, except for the parts that don't have a STEP file associated with them.  Under Export->MCAD->STEP, I check the boxes for "Parts with STEP models" and "Parts without STEP models".  I've got 3 or 4 parts that I was unable to find proper 3D models for them.  Therefore, I have assigned a PACKAGE_HEIGHT_MAX value to the package shape on PACKAGE_GEOMETRY->PLACE_BOUND_TOP.  However, for these parts missing STEP files, when exported, they seem to default to the 'Default symbol height" instead of the PACKAGE_HEIGHT_MAX.  If I envoke the 3D Viewer in PCB Editor, these parts look fine (small squares/rectangles of appropriate height), but when exporting a STEP, they go off the rails.

Any thoughts as to a setting or something that I'm missing?  The export settings seem pretty explicit that it should support both parts with and without STEP mappings, but I must have something setup wrong.

Thanks.