Hi
The above error is still showing up even when i have setup dbc file again.
Also, some of the parts in Part Manager window do not have any part number assigned to them.
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Error: Table name not found in dbc (CIP)
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Custom reports - how do I get a list of net pins
I am trying to generate a custom report similar to the Net List report.
Where do I find the actual file used for the report ?
Or how do I get a list of a net pins in a custom report ?
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Place Arduino Uno or ATmega328 part in Capture
Hi. I'm new to the forum, so I'm not sure if I'm posting in the correct place. I'm trying to figure out where to find an Arduino Uno or ATmega328P to place in my schematic. Is this possible, and if so, can someone point me in the right direction?
Thanks in advance.
RichC
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How to take over a design from an outsource
My company outsourced a design of a complex board and now we would like to take over the design for ourselves. Problem is the contractor database part numbers don't match up with our part numbers even the parts are exactly the same. What is the best way to map our parts to there parts and make this board connected to our database?
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DRC error: route keepout spacing
hello
i have a route keepout spacing error.
i do know that i can allow "vias", "routes" (clines), "pins" and "shapes" in the keepout shape area by changing the shape properties.
but i get this "line to keepout spacing" error as i place a text into a keepout area.
is there any way to allow a text or a line into a keepout shape area by changing the shape properties?
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Write protect a Cadence Capture project
Hi,
Is there a good way to write protect projects in Cadence Capture? I like to have multiple previous projects open to copy paste from etc. but always worried will save some unintentional changes.
Maybe there exist some lock function in preferences for the project?
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find filter control
hello
is there any way to control what items to display on the find filter?
currently as default, there are so many items on the design object find filter that are not in use so i want to remove the items that i do not use, for instance, groups, lines, bond wires, other segs, ratsnests, and rat ts.
i was able to control what to display in the "visibility" section by modifying the visibility pane in color dialog so hopefully i can do the same in the "find" section.
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Footprint
Hi,
How to draw a gold finger connector in orcad 17.2??
Kindly guide me.Thanks in advance
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VIA selection for Automatic Router
Hi,
I am using the Autorouter and by setting the constraint of Min Line Width inside CM I can control the width of the trace for a specific Net, but how can I control what VIA a specific Net shall use? I am trying to set it inside the CM but it keeps using the VIA it had pre-selected before.
Also is it possible to define a certain Net should have pass with for example 3 Vias?
Thanks.
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Replace Blind Via with Blind/Buried Stacked Via?
Hey guys,
I have a 10 layer design with a Blind 22/8 via from layers 1-9. I need to have a blind micro via from L1-L2 on the top of this via. Is there a way to do a global replace of my L1-L9 via with my stacked L1-L2+L2-L9 via?
I know I can do a global replace of the L1-L9 via with the L2-L9 via, but that will leave a disconnect from L1-L2. I currently have roughly 27,000 of these vias in the design so finding a global replace would be a bit of a timesaver.
Thanks in advance!
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OrCAD Capture 17.2 Start Screen
I'm looking for the way to disable the OrCAD schematic start screen. In version 16.5 there used to be a way to do it by editing some extended preferences. However that part of the menu system changed in version 17. How do we do we disable the start screen now? I did a search in help on "extended preferences" and got nothing.
Old method (V16.x):
1. Open any design in Capture.
2. From the Menu bar, select "Accessories \ Cadence Tcl/Tk Utilities \ Utilities".
3. In the "Tcl/Tk Applications Dashboard", select 'Extended Preferences' and press the Launch button.
4. In the column 'Settings', uncheck "Load web page on startup" and then the 'OK' button at the bottom.
Thanks.
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OrCAD User Assigned Reference Unset
In the last few years OrCAD schematic added a feature where when a user edits the reference designator of a part it underlines it to show its been edited. I really wish it would not do this. To make the underlining go away I have to select the part, right click, chose User Assigned Reference, and then Unset. In part of my job I have to copy several pages of schematics and then change all the ref deses on all the copied pages. This User Assigned Reference is a major PITA, easily doubling the effort of my job.
Two questions:
- Can I stop OrCAD from showing Unset User Assigned References? Maybe an off switch somewhere? This feature causes me far more problems than it solves.
- Is there a way to group edit User Assigned References? I could select many parts and quickly edit this setting on all as a group. This would be a good compromise.
Thanks.
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DRC Error - SMD Pin to SMD Pin
Hi,
I run into this DRC error and wonder if anyone has experienced the same and know how to correct it. I am using OrCAD PCB Designer Standard and OrCAD Capture 17.2 for this project (and I am new to this PCB Designer).
This section of the board consists of 6 relays (Panasonic JS1-5V-F) driven by two ULN2003 SOIC-16 chips. For clarity, the net names are as follows:
- Control signals from CPU to ULN2003 inputs: OUTPUT[1..6] with OUTPUT[1,2] go to one ULN2003 and the rest to the second ULN2003 (and their outputs drive the relay coils)... trace thickness 10mils
- Relay contacts: OUTPUT_C[1..6], OUTPUT_NC[1..6], and OUTPUT_NO[1..6] (these three pins connect directly to the 3-pin terminal blocks)... trace thickness 150mils
In the constraint manager, I initially assigned a 50 mil clearance for all these OUTPUT nets across various columns (Line to >>, SMD Pin to >>, etc...) using Spacing CSet. When I started routing the OUTPUT[1..6] nets, various DRC errors popped up at the ULN2003 chips. I realized my mistake by having 50mils clearance for all OUTPUT[1..6] nets. I then removed these nets from the class and used default values of 10mils clearance for all instead.
This cleared a few errors, however, the SMD Pin to SMD Pin DRC errors remain with P><P indicators in between ULN2003 pads as well as capacitor and resistors pads on the associated nets. I deleted partial traces to the chips and rerouted these nets. This cleared the errors on the first ULN2003 chip with OUTPUT[1,2]. Strangely, these errors remain for the OUTPUT[3..6] nets on the second ULN2003.
When I opened the constraint manager to look for more details, the DRC Spacing window says 10 mils for Required and 18.5 mils for Actual (which is correct for the ULN2003 footprint I use - 1.27mm pitch and 0.8mm pad width). This should not generate any errors. It seems the software does not use the updated 10mils clearance for errors checking even it logs the value correctly. Closing and opening the software does not make any difference. The change that I made maybe corrupts the design database somehow?. I am a bit lost at this time. I just wonder if anyone has any idea how to resolve this.
I have one more question unrelated to this error. Currently I have a 150 mil trace for each of the OUTPUT_C/_NC/_NO[1..6] nets on the top layer. I would like to have 300mil in total for each trace (for higher current) by adding another 150mil trace on the bottom layer. How do I do that?. I have tried using Shape/Polygon connecting the two pins and assigned the same net name. It seems to work but when I draw the polygon near the pin center, the software adds something like a + sign at the pin with 150 mil thick, which is very messy. I tried to Add/Line etch with 150mils but cannot assign net to it. Line is much cleaner and easier to trace over the existing routes.
Any hint/help would be very much appreciated. Thanks.
TC
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Frustration in getting bugs fixed
Hi all,
I have submitted a number of CCR's with what I find are bugs in the software only to have the CCR placed in the inactive pile. For me this means it will probably never get fixed. Others are left open an never seem to get fixed after a year of being open.
I spend a lot of time documenting the problem so they can reproduce it only to have them consider it an enhancement and maybe it will get fixed.
it is obvious that the R&D department never sits with a user and see the frustration I go thru trying to find a workaround for the obvious bugs and the extra time I have to spend that could
be used to be more productive.
EMA EDA and the tech support in India are good when the problem is something they can provide an answer but terrible in trying to resolve issues that require software fixes. Not there problem as they only submit the problems to R&D.
I am curious is anyone else sees programs in the software and submits CCR's only to see then not get fixed. Or do you just live with them ?
Have you have any luck trying to get issues resolved ?
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After updating the OrCAD CIP Server to v17.2.13.4 the server no longer starts.
My channel partner, EMA Design Automation, recommended I update my CIP Server and Client to the latest version. After the update, CIP Server won't start.
This is the information the CIP tab displays in Capture CIS:
ERROR [08001] [Microsoft][ODBC SQL Server Driver][DBNETLIB]SQL Server does not exist or access denied.
ERROR [01000] [Microsoft][ODBC SQL Server Driver][DBNETLIB]ConnectionOpen (Connect()).
Description: An unhandled exception occurred during the execution of the current web request. Please review the stack trace for more information about the error and where it originated in the code.
Exception Details: System.Data.Odbc.OdbcException: ERROR [08001] [Microsoft][ODBC SQL Server Driver][DBNETLIB]SQL Server does not exist or access denied.
ERROR [01000] [Microsoft][ODBC SQL Server Driver][DBNETLIB]ConnectionOpen (Connect()).
Source Error:
Line 31:
Line 32: function openAbout(event) {
Line 33: var aboutConfig = { title: '@Html.Raw(CIPProperties.ProductTitle)', serverVersion: '@CIPProperties.Version', databaseVersion: '@Global.Configuration.DatabaseVersion' };
Line 34: event.preventDefault();
Line 35: ema.cip.showAboutDialog(aboutConfig);
Source File: c:\Cadence\CIP-E\CIP\Views\Shared\_Layout.cshtml Line: 33
Stack Trace:
[OdbcException (0x80131937): ERROR [08001] [Microsoft][ODBC SQL Server Driver][DBNETLIB]SQL Server does not exist or access denied.
ERROR [01000] [Microsoft][ODBC SQL Server Driver][DBNETLIB]ConnectionOpen (Connect()).]
EMA.CIP.CIPODBCDatabaseAdapter.ExecuteReader(OdbcCommand cmd) +168
EMA.CIP.CIPODBCDatabaseAdapter.SelectFromTable(String tableID, List`1 selectFieldIDs, List`1 whereFieldIDs, List`1 parameters, Boolean distinct) +1309
EMA.CIP.CIPODBCDatabaseAdapter.GetProperty(String property, String defaultValue) +232
EMA.CIP.CIPConfiguration.LoadFromDatabase(String[] roles, ICIPDatabase databaseAdapter) +272
EMA.CIP.Global.get_Configuration() +808
ASP._Page_Views_Shared__Layout_cshtml.Execute() in c:\Cadence\CIP-E\CIP\Views\Shared\_Layout.cshtml:33
System.Web.WebPages.WebPageBase.ExecutePageHierarchy() +252
System.Web.Mvc.WebViewPage.ExecutePageHierarchy() +148
System.Web.WebPages.WebPageBase.ExecutePageHierarchy(WebPageContext pageContext, TextWriter writer, WebPageRenderingBase startPage) +122
System.Web.WebPages.<>c__DisplayClass40_0.<RenderPageCore>b__0(TextWriter writer) +309
System.Web.WebPages.WebPageBase.Write(HelperResult result) +108
System.Web.WebPages.WebPageBase.RenderSurrounding(String partialViewName, Action`1 body) +89
System.Web.WebPages.WebPageBase.PopContext() +310
System.Web.Mvc.ViewResultBase.ExecuteResult(ControllerContext context) +375
System.Web.Mvc.ControllerActionInvoker.InvokeActionResultFilterRecursive(IList`1 filters, Int32 filterIndex, ResultExecutingContext preContext, ControllerContext controllerContext, ActionResult actionResult) +88
System.Web.Mvc.ControllerActionInvoker.InvokeActionResultFilterRecursive(IList`1 filters, Int32 filterIndex, ResultExecutingContext preContext, ControllerContext controllerContext, ActionResult actionResult) +775
System.Web.Mvc.ControllerActionInvoker.InvokeActionResultWithFilters(ControllerContext controllerContext, IList`1 filters, ActionResult actionResult) +81
System.Web.Mvc.Async.<>c__DisplayClass3_1.<BeginInvokeAction>b__5(IAsyncResult asyncResult) +188
System.Web.Mvc.Async.AsyncControllerActionInvoker.EndInvokeAction(IAsyncResult asyncResult) +38
System.Web.Mvc.<>c.<BeginExecuteCore>b__152_1(IAsyncResult asyncResult, ExecuteCoreState innerState) +26
System.Web.Mvc.Async.WrappedAsyncVoid`1.CallEndDelegate(IAsyncResult asyncResult) +68
System.Web.Mvc.Controller.EndExecuteCore(IAsyncResult asyncResult) +52
System.Web.Mvc.Async.WrappedAsyncVoid`1.CallEndDelegate(IAsyncResult asyncResult) +39
System.Web.Mvc.Controller.EndExecute(IAsyncResult asyncResult) +38
System.Web.Mvc.<>c.<BeginProcessRequest>b__20_1(IAsyncResult asyncResult, ProcessRequestState innerState) +40
System.Web.Mvc.Async.WrappedAsyncVoid`1.CallEndDelegate(IAsyncResult asyncResult) +68
System.Web.Mvc.MvcHandler.EndProcessRequest(IAsyncResult asyncResult) +38
System.Web.CallHandlerExecutionStep.System.Web.HttpApplication.IExecutionStep.Execute() +602
System.Web.HttpApplication.ExecuteStepImpl(IExecutionStep step) +195
System.Web.HttpApplication.ExecuteStep(IExecutionStep step, Boolean& completedSynchronously) +128
--------------------------------------------------------------------------------
Version Information: Microsoft .NET Framework Version:4.0.30319; ASP.NET Version:4.7.3429.0
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Creating Netlist Error
I am trying to create a new netlist from a file that I modified in OrCAD capture. When I run tools > create netlist the following error occurs: Error: Schematic supports creating XNets for passive devices and for devices having XNET_PINS properties but the Layout will create XNets only for devices having XNET_PINS properties. Change setting in Layout or Schematic, re-generate files, and re-run the flow.
I am modifying a previous .brd version and I don't understand how to change the settings in Allegro PCB to get rid of this error.
Thanks for the help
Jeff
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Changing Line Width of a Trace in a Net without DRC Errors
Hi,
I would like to know a way to change the line width of a trace within a larger net without DRC errors.
I have a net with 100mil line width assigned to it. There are several traces branching off from this main 100mil line that I want only 8mil thick (e.g. pull-up resistors/decoupling caps). When I manually change the line width for these traces (and they are long traces), I get millions of L><W error markers on them. Is there a proper way to do this in OrCAD PCB Designer Standard 17.2 version (and I am new to it).
Any help would be greatly appreciated. Thanks.
TC
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Netlist generation _Ocard -Allegro with diferent reference designator)
One our Costumer has the ownership of SCH, but in the latest SCH update that he sent, he changed all the ref-des (all the placemen in the layout was a swapped or changed).
There is any way to load the SCH netlist in allegro keeping the current ref-des in the layout and without affecting the placement? Thank you in adavnce
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Update net names and net groups in an existing design
Hi Cadence,
I need to rename some nets in my design and they are part of netgroups I created previously. However it seems renaming netgroup instance name is not that easy, since there is no rename button can be used. When I tried to create new net groups and remove the old ones, I got the error ORCAP-1828:
I am pretty sure that this netgroup has been removed from my hierarchical design, but I can still find it in the design cache, Netgroup Definitions, cleanup cache didn't work.
Any comments helpful will be appreciated, my goal is to keep the previous PCB design, I just want to update the net names.
Thanks!
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Regarding making of library in allegro_design_entry_HDL?
In allegro_design_entry_HDL as libraries i am getting and that i have created using Padstack editor is of format .jrl, .psm, .tag, .log, .dra, .psm, .dra.lck. But in Allegro_design_entry_HDL the libraries are divided in three folders. Chips , entity, sym_1
Inside chip it is .prt and .tag
Inside entity it is .tag, .db, .v, .vhd, .vlog004u.sir
inside Sym_1 it is .tag, .css, .lck
So i am not getting how the library for allegro_design_entry_HDL is created.?Please help me out?
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