Production-Standard General-Use Microcontrollers?

September 17, 2019, 4:47 am

≫ Next: Regarding available libraries for allegro_design_entry_HDl on internet

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(I am a very new newbie newb)

So it's my understanding that something like the ESP8266 is meant only to be a development/prototyping board, and that traditionally, the next step would be to design and manufacture your own PCB. However, my design is incredibly simple, only requiring wi-fi and the ability to control approximately 300-400 individually addressable LEDs.

This would be a small volume product, and I find it difficult to believe that something so simple requires custom-made PCBs. Is there such a thing as a general-purpose production-grade microcontroller? It seems to me that if you can create something like an ESP, you should be able to create something similar that meets the standards necessary to be safely included in a commercial product.

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Regarding available libraries for allegro_design_entry_HDl on internet

September 17, 2019, 5:45 am

≫ Next: route keepin

≪ Previous: Production-Standard General-Use Microcontrollers?

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As i am very new to this software i am little bit confused in it. I was able to create the library for allegro entry HDL but not able get the already available libraries on internet. As the libraries i am finding is of extension

.dra, .pad , .ssm, .psm, but this libraries are not suitable for cadence. So what to do?

Is there any site where i can find bulk of libraries for Allegro design entry HDL?

route keepin

September 17, 2019, 8:53 pm

≫ Next: Deleting layers on a board with laser vias and core vias.

≪ Previous: Regarding available libraries for allegro_design_entry_HDl on internet

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hello

is there any way to create a different route keepin for a different layers?

currently as default, i can set up only one route keepin for all layers as "though all."

i have two substrates put together in one design file and the two substrates have a diferent size so i want to set up a different route keepin for each substrate.

Deleting layers on a board with laser vias and core vias.

September 18, 2019, 6:27 pm

≫ Next: Assembly drawing PDF export

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If I have a 12 layer board with 1-2 2-3 3-4 laser vias 4-9 core via and 9-10 10-11 and 11 to 12 laser vias , if I delete layers 6 and 7 what does the software do to the laser and core vias  ?

Assembly drawing PDF export

September 19, 2019, 11:26 am

≫ Next: Capacitive Touch Button

≪ Previous: Deleting layers on a board with laser vias and core vias.

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Hi,

I'm using OrCAD PCB designer professional v17.2. When I go to Export -> PDF, it gives me licensing error. I'm already using professional version and I have no problem when I generate PDF schematic. Can somebody let me know why orcad people dont have this basic functionality ?

Capacitive Touch Button

September 20, 2019, 2:51 pm

≫ Next: X10 Control code generator - First Line Voltage project

≪ Previous: Assembly drawing PDF export

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Hi all,

I am trying to make a 2 layer board with a very simple capacitive touch button with a via pin. I made a circular shape on the top plane and added the pin but I am getting DRC error: thru pin to shape spacing.

I tried editing the constraint value to 0, and also tried a connector with a via instead, but I need the via to be my pin and I can't get rid of the DRC error.

Can someone please help me out?

X10 Control code generator - First Line Voltage project

September 21, 2019, 2:21 pm

≫ Next: How to check copper to copper clearance?

≪ Previous: Capacitive Touch Button

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This is my first time trying something that's directly connected to the mains. I'm building this to add in to my dispenser controller. The 6 pin header near the DIP switches and microcontroller are just a programming header for the ATMega. The always on 120VAC is the trace that runs along the top of the board, and is pin 1 on the two screw terminal blocks at the top left. Pin 2 on the terminal blocks is switched hot. Pin 3 is the neutral, and reference ground within the circuit. I used both the top and bottom layers to connect the two screw terminal blocks to maximize current carrying capabilities.

How to check copper to copper clearance?

September 22, 2019, 7:38 pm

≫ Next: Where is the link to download cadence trial version software?

≪ Previous: X10 Control code generator - First Line Voltage project

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I use OrCAD PCB Designer Professional 17.2.

My PCB partners require 6 mil clearance between copper objects.

The board has 4 layers. I use a through via array to connect a plane on layer 3 and other on layer 4. To ensure 6 mil clearance, I must add plane on layer 1 and 2.

If I omit layer 1, I want the layout to notice me the error.

Question is How to set up constraint to solve the above problem?

Please refer the below picture.

Layer 4

Layer 3

Layer 2

Layer 1

Thanks,

Tom

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Where is the link to download cadence trial version software?

September 23, 2019, 5:52 am

≫ Next: Rigid Flex Capture

≪ Previous: How to check copper to copper clearance?

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I hope to learn to use cadence for schematic and PCB design (not just for view). But I do not find the link of the trial version of the software. Where I can find the trial version?

Thank you

Rigid Flex Capture

September 23, 2019, 6:57 am

≫ Next: Regarding Packages in Allegro PCB Librarian

≪ Previous: Where is the link to download cadence trial version software?

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Hi 

I am designing a rigid flex board where a 20pin connector should sit on the rigid side and all the connections from this connector should go to

the flex pcb where the pads at the end of this flex pcb will be exposed so that they could be soldered later on.  Is it all that needs to be done in capture or something missing 

to define pads.

Regarding Packages in Allegro PCB Librarian

September 24, 2019, 4:28 am

≫ Next: Ultra librarian setup

≪ Previous: Rigid Flex Capture

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I want to create a 32 pin qfn package using allegro pcb librarian but it has not shown any option regarding to in JEDEC Type , How to get a qfn package?

Ultra librarian setup

September 24, 2019, 6:41 am

≫ Next: Converting ,brd to .mcm

≪ Previous: Regarding Packages in Allegro PCB Librarian

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So, I've screwed up my Ultra librarian setup somehow and don't recall what I did. This is the error message: It's the same regardless of what package I'm trying to create.

Converting ,brd to .mcm

September 24, 2019, 9:26 am

≫ Next: Intelligent PDF using Nitro Pro - Anyone know how to setup this up?

≪ Previous: Ultra librarian setup

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Hello Cadence, 

I have a .brd file and I want to use Cadence Package designer, which requires the file to be a .mcm file. What is the best way to convert the .brd file to a .mcm file?

Thanks,

Liz

Intelligent PDF using Nitro Pro - Anyone know how to setup this up?

September 24, 2019, 12:57 pm

≫ Next: How to use page names in custom text?

≪ Previous: Converting ,brd to .mcm

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Our wonderful "IT" organization is removing Adobe Acrobat and replacing the tool with Nitro Pro 12.

(Version of Capture aka Orcad is 16.6)

We are able to create the 3 ps files using the tcl script, but we have been unable to figure out how to post process these in Nirto.  I understand this is not a Cadence issue, but I am hoping some one in the community has figured this out.

BTW they have taken away our Local Admin rights and our hands are tied.......

Kind Regards,

Wild.

How to use page names in custom text?

September 25, 2019, 2:23 am

≫ Next: How to get drop down options for the value field in Capture CIS

≪ Previous: Intelligent PDF using Nitro Pro - Anyone know how to setup this up?

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In Allegro Design Entry HDL,

I'd like to use the current page name in a custom text so that when I change a page name on Hierarchy View, It will be automatically changed on the same page schematic. Is there a way to do it?

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How to get drop down options for the value field in Capture CIS

September 26, 2019, 5:01 am

≫ Next: Issue in creating the variant BOMs by customizing the value field

≪ Previous: How to use page names in custom text?

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I am using OrCAD Capture CIS 17.2 059. I am facing a issue in creating a drop down in access based database of capture CIS.

In the schematic field of access worksheet if it is mentioned as discrete\CAPACITOR NON-POL,discrete\CAP NP,SMALL CAP,analog\C in CIS explorer window I am able to get the drop down to select which schematic part I

want to place in schematics but the same isn't happening for the value field when mentioned as any of the formats 10K,20K or 10K\20K or 10K/20K

The reason why I need this is some cases I may use resistor of value 1K and in some cases 10K. I dont want to create another copy in database just for the change in value.

Issue in creating the variant BOMs by customizing the value field

September 26, 2019, 5:12 am

≫ Next: BUG - Allegro PCB Editor - Board 3D STEP model

≪ Previous: How to get drop down options for the value field in Capture CIS

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I am using OrCAD Capture CIS 17.2 059. I am facing a issue in customizing variant BOM.

I have a design where the component holds two different values say for example inductor L1 has 12.8mH and another case 1.8uH and for the same I want create a BOM variants V1 and V2.

The issue is I want to create a BOM v1 which has L1 value 12.8mH and V2 having 1.8uH. I don't want to do any manipulation to design or database. Is there any method to do so ?? 

BUG - Allegro PCB Editor - Board 3D STEP model

September 26, 2019, 12:06 am

≫ Next: ECAD/MCAD / IDX IDF export

≪ Previous: Issue in creating the variant BOMs by customizing the value field

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Good morning, I have recently found an apparent bug in Allegro PCB Designer 17.2 with HF 059.

As per new 17.2, board outline has to be designed on layer Design_Outline in Board_Geometry. For annotation/guide I use layer Outline to first import DXF and then compose a shape on Design_Outline from Outline layer.

This is working ok in terms of showing 3D model inside Allegro by clicking 3D button. But when I export STEP Model from File menu, not only Design_Outline is exported but also Outline layer, producing an wrong STEP file.

Hope this get's fixed in the new HF 060.

Kind regards

ECAD/MCAD / IDX IDF export

September 26, 2019, 7:12 am

≫ Next: silkscreen not associated with a pcb symbol

≪ Previous: BUG - Allegro PCB Editor - Board 3D STEP model

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hey,

I try to setup a collaboration between ECAD and MCAD. So far it works but the big problem is, that all parts on the back side (only on the back side) are twisted (180°).

If I export the PCB as a IDF, everything is fine. If I export this as IDX everything is twisted.

Is there an option so I can turn this off/on?

Thanks

Left pic: IDF export=right see coordinates

right pic: IDX export=wrong

ORCAD 17.2

Solidworks 2017 / CircuitWorks

silkscreen not associated with a pcb symbol

September 26, 2019, 9:03 am

≫ Next: ultra librarian plug in for orcad

≪ Previous: ECAD/MCAD / IDX IDF export

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What's the best way to search for all elements (lines, shapes, text, etc) in package geometry/silkscreen class/subclass that were added in the board level?