Hello,
I'm working with ORCAD PCB 17.2.
I would like to select all the vias on the net GND.
Please could you help me.
Many thanks
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Select vias GND
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Select VIAS on a same net
Hello,
I'm working with ORCAD PCB 17.2.
I would like to select all the vias on the net GND.
Please could you help me.
Many thanks
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Component Device Pin Number Mismatch; Cannot Replace
Hi All,
I have been trying to translate a board made in Altium to OrCAD. When making the Netlist, I received the warning:
#3 WARNING(SPMHNI-184): Device library warning detected.
WARNING: U11 component device pin number mismatch; cannot replace.
The part is a simple 4 pin regulator. Both the schematic symbol and the PCB symbol have 4 pins, as far as I can tell. How can I resolve this?
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Stream Out Dielectric Vias
Hello,
I am new to Allegro and trying to create a GDS file representing the conductors in the PCB design. Using the stream out functionality I can get the etch and vias for each conductor layer, but I also need the vias traveling through the dielectric, so I can build a 3D model of the conductor geometry.
If I write a conversion file that maps a GDS layer to each conductor layer's vias I can't separate the vias traveling upwards and downwards into the two adjacent dielectric layers. The vias also do not show up in dielectric layers.
How can I create a GDS stream layer that describes the vias in that dielectric layer?
Regards,
D
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Donut pad and shapes transparency
Hello
I'm working with 17.2 release.
I've a symbol with a donut pad.
In Pad Editor it has Donut Geometry (no shape)
Why the pad disappears if I set 0% in shapes transparency???? It isn't a shape!! It's a pad!!
Is it a bug?
Regards
Stefano
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Module with homogeneous part does not optimize package
I have created a module that includes a single opamp which comes in a quad package (i.e. there are 4 identical opamps in one IC, specified as different sections in part developer).
Now I need to place 4 of such modules in my design.
In my past experience, once placing several modules, the packager would recognize that the opamps can be optimized and use a single IC every four modules. However in the current design this is not happening: each module is assigned a unique IC (so IC1, IC2, IC3, IC4) and then only one of the opamps in the IC is used in every module. This is clearly not ideal as it means using 4 times the number of required ICs.
I have tried to descend into a module and specify the section to use, but the change propagates to all of the other modules: if I descend in module 2 and specify to use section 2, then all other modules use section 2 and I am back to the starting point.
I have read various documentation about modules and packagin but I still can not locate why this is happening.
Is there a trick/setting to tell the packager to optimize the ICs to use the minimum amount of components?
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Metadata
Hi Everyone,
Is there metadata in schematic or PCB files? And if so, how do I view it and can it be edited or removed?
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Hole to Line spacing not working
Constraints:
Constraints are enabled:
But some other constraint seems to be active:
The pink color is the hole and the kind of shaded part in the middle is the pad, which will be removed by the drill. So it's a NPTH.
Any ideas why I can route as close as 0.15 mm to the hole and not 0.3 mm?
Padstack data:
type: Through Pin
units: mm
decimal places: 4
Hole data
geometry: Circle
size: 3.3000
offset: (0.0000, 0.0000)
tolerance: positive=0.0000 negative=0.0000
plating: Non-plated
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Regarding deleting X-Net property added for a signal in PCB board file
Hi,
Iam using 17.2version Venture pcb design tool. I need to delete an X-Net property which had been added for a particular net. Can you guide me on fixing this issue.
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Visibility,options,find tabs anchoring
Hello all,
I vaguely remember able to anchor the three tabs ( Visibility,options,find ) in the style below:
However I cant seem to get this going in my version of allegro 17.2, Currently the visibility tab isnt anchored and I wish all three tabs to be anchors. Essentially I wish to be able to anchor the tabs in the follow style on the left:
Any help on this issue would be be of great help as a I cant for the life of me to get them all to anchor in the above style. Thanks!
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CIP in Orcad 17.4
I have installed Orcad 17.4 and is currently learning the new feature with this update.
However I am unable to open CIP in orcad. CIS works okay.
To open CIP I have to open it in my internet browser and I would like to open it in orcad like my 17.2 version.
One more thing anyone in the UK noticed that RS components have disappeared from distributor search
Is there any one out there having the same sort of difficulties as I am
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Re : I2C Routing SCL,SDA as 100ohm differential pair
Hi Folks,
I have done many designs with I2C and routed SCL,SDA as 50ohm SE lines.Recently I have done this as 100ohm diff pair for one of our customer. Whether it is ok in-terms of functionality?
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Why 50ohm,90ohm,100ohm transmission line?
Hi ,
In pcb design , when designing the transmission line, we particularly choosing 50ohm for SE, 90ohm for USB, 100ohm for differential.Based on the co-axial cable characteristic impedance is 50ohm, we are designing same in PCB. Whether loss will be less in there particular impedance range? Why cant we design USB in 100ohm instead of 90ohm?
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unassigned nets
hello
is there a way to remove all unassigned nets at once from the design file?
i do know i can remove an unassigned net one by one.
but i would like to be able to remove them all at once like purging all unused padstacks.
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Updating a shape takes forever
I have a GND shape, covering the entire top plane, which is giving me a headache. Manually updating the shape or any other edit that indirectly updates the shape takes forever. Well, it takes at least between 30 and 60 seconds and Allegro becomes unresponsive during that time. Allegro even shows as Not Responding in Windows Task Manager.
What can cause this behavior? I suspect that there's some setting in Allegro somewhere that should be changed.
I'm using Allegro 17.2 and Windows 10. Computer has an Intel Xeon E3-1505M v6 @ 3.00GHz CPU and has 32 GB RAM so it should be fast enough.
It's a medium sized board as shown below.
/F
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Forcing an NC pin to connect to a net
I have a symbol with pins that don't connect to any net. Can I force them to connect to a net in Allegro PCB designer? This would of course be best to do in the schematics, but the library symbol don't have the NC pins and the library is manged from elsewhere...
What I want is the GND shape to pour over the pins with no net names:
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How to solve the problem INFO(ORCAP-2242): Checking Incorrect Pin Group Assignment
INFO(ORCAP-2242): Checking Incorrect Pin Group Assignment
Report for Invalid References
Report for Duplicate References
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Checking Entire Design: PCB_DESIGN
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Checking Entire Design: PCB_DESIGN
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Checking Power Pin Visibility
Checking Normal Convert View Sync
INFO(ORCAP-36105): Checking Missing Pin Numbers
INFO(ORCAP-36105): Checking Missing Pin Numbers
Checking Device with Zero pins
INFO(ORCAP-36101): Checking Missing PCB Footprint Property
INFO(ORCAP-36101): Checking Missing PCB Footprint Property
Checking Name Property for Hierarchical Instances
INFO(ORCAP-2211): Check High Speed Properties Syntax
INFO(ORCAP-2212): Check Power Ground Mismatch
Reporting Unused Refdes in multiple part packages
How to solve the problem?
Help me pls
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Locating drill hole
Hi
In my customize drill table window, it is showing that there are 2 drill holes of 0.2mm size but i cannot locate these holes on my board.
Also the find window is not helping in finding these. As far as i could remember i have not used them. How can i find these holes on
my board?
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Selecting Part in Capture selects Component in PCB Designer, but not vice versa
I have V17.2, and when I select a symbol in Capture, Editor zooms in and highlights the part. However, there is no backwards linkage apparantly. When I select a part in Designer, it does nothing in Capture. When I was using V15.7 a few years ago, it had this functionality, but not now. Is this a feature, and how can I enable it?
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Design Rule check grayed out in Orcad 16.6
Hi All, I made a schematic project using Orcad 16.6. However when I try to enable "Run physical Rules" in design rule check, it is grayed out. Please see pic below. Also I am unable to change the file name of the report file. I checked if the folder is having any "Read Only" permissions.But there is nothing set.I am unable to figure out the reason why.
Can someone please let me know how to solve this problem ?
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