Good Day, I'm new to Cadence and I'm using Allegro PCB Design Entry HDL. but I am having some error and I cannot open my schematic for now.
And I got to the folder and open the notepad. This error
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Warning: Attribute "CDS_DI_CONTROL_MASK" is not defined. Failed to create "CDS_DI_CONTROL_MASK" attribute for object Design "ltc_board".
Please someone advise me what do i need to do.
Is anyone familiar with this error code? We've somehow lost 2/3 of the schematics that we had the day before.
Thanks
Greetings all,
I have created a footprint with two separate padstacks. Each padstack is using flash files for both the paste mask and solder mask as each requires multiple openings for each pad. The flash files look good and even viewing the completed .DRA file I can see that the solder and paste masks look good. The issue is that when I netlist and place the part into the board file both the solder and paste mask layers are now identical to the single copper pad. They no longer contain multiple shapes, but just the one solid shape the same size as the copper pad.
What am I missing?
Thanks in advance.
I am import a Altium hierarchical design to Orcad capture, it completed successfully, but it won't generate netlist. because there are lot of
#1 ERROR(ORCAP-36032): Duplicate Reference Designator U10A: accumCompare, Page1 (6.50, 2.50).
#2 ERROR(ORCAP-36032): Duplicate Reference Designator U10B: accumCompare, Page1 (0.90, 7.20).
on the PCB the designator are U10_1 and U10_2.
I know if annotate the schematic, it will assign the duplicate reference designator with different ones. but how to match it with the PCB.
seems it is a very straight forward problem. because I couldn't see a lot user ask this question one the forums.
do I have to manually update the designator to match that on the PCB?
hello
i would like to set up the constraints for diff pairs.
for clines in general, the space is 100um.
the space between clines of a diff pair is 50um.
is there a way to set up a gap between a cline of one of the diff pair and a cline of a different net which is GND?
I would like to set up the gap as 150um.
i have created two spacing sets, one for 100um in general and the other is for diff pairs, 50um.
do i need to create another set for 150um?
i do not know how to set up the constraints for diff pair nets and GND.
Is there a way to set Pad Editor to always use mm as default? I am always making the footprints in mm but sometimes I forget to set it at startup of pad editor and then have to go back and redo the pads. Would be good if its possible to set mm to be used as default.
Thanks.
Hello ,
I am facing a serious issue with x net .
I have not set any SI model for x-nets but its showing random group of xnets , how to remove this ?
some of the power nets gets merged with signal net and showing as xnet , its not taking the constraint set for signal . I tried different method but unable to solve
I am not sure whether its imported from schematic library or not !
Please refer attachment .
I use
Thanks
Girish
I am using Allegro 16.6V. I am trying to enter two separate pages of schematic under a single schematic folder. I need to create a single netlist and I need to have reference designators of each page to begin at Number 1.
Can somebody tell me the steps I need to follow?
Thanks In advance
Hi,
Where can I find a FORM list for PCB editor 17.2.
Because I'm looking for the drill customization FORM's name.
Florent
Hello. I did a schematic design in OrCAD Capture as part of OrCAD PCB Designer version 17.2. In that design, I used many of the built in schematic symbol libraries with a library path on the C: drive (with the version 17.2 in the path). I then upgraded the software version to 17.4, and want to edit the design that was started in 17.2. I'd like to migrate the design's built in libraries to the new 17.4 version of them. How do I do this?
Thanks,
Gabe
I have single pin parts that I added in the schematic as test points and the footprint is an SMT pad. Now I am trying to add manufacturing test points in the layout but I cannot get the tool to recognize those pads as test points or add them. I only want test points on the bottom side, which is where all of my SMT test points are. Neither manual or automatic works. The frequent error I get is "Pad is under a pin". I tried turning off all restrictions. I want this pin to become the test point. I was able to get vias to be added as test points on those nets but that is not what I want. I am out of ideas.
Our flow is using DxDesigner schematic PCB interface to Allegro PCB editor. But lately we want to use the PAD VX.2.5 (upgrade PC also to windows 10). Now we encounter that once the Pads VX 2.5 export ".tel" file it wont change the Allegro board file automatically. We can import it manually and we don't experience any error. Can anyone educate me on my concern. Is there handshake restriction in windows 10 that prevents the Pads VX 2.5 to modify the Allegro board file automatically?
Hi
I use the XCVU19P-FSVA3824 in my new design, but I can't find it in FPGA system planner . my tool version is SPB17.2 (S056). Can you tell me which version include VU19P-FSVA3824 in FPGA system planner. Thanks!
Is there a way to disable Allegro / PCB designer to constantly create log files for every little thing one does?
I noticed that whenever i modify something about a footprint or do other activities , Allegro / PCB designer creates log files.
I keep manually removing them to reduce clutter , but i was wondering if loging could be disabled.
I am using the Latest Allegro PCB designer 17.4 S003. I want to calculate the parasitics of trace and used the options available within Allegro and found that results displayed on the parasitic window and impedance workflow analysis window are different. Below are the results.
The query is how can there be two different values for a single trace?
When I use Display - a parasitic option the results of RLC is as below
TOP CONNECT LINE on network DATA4Impedance : 81.142000 ohmInductance : 25.880200 nHCapacitance : 3.930760 pF (to SHIELD LAYER)Prop Delay : 0.31895 nsResistance : 242.521000 mOhm
But when I perform Impedance analysis using workflow manager the results are as follows
| Net Name | Vias | No Ref | Max | Min | Typ | Max | Min | Typ | Length | Delay(ns) | R(mOhm) | L(nH) | C(pF) |
| DATA4 | 1 | 0 | 79.8 | 79.8 | 79.8 | 100 | 100 | 100 | 3869.53 | 0.564 | 426.089 | 45.035 | 7.066 |
How do i redock the Global Navigation Window in the HDL schematic?
Hi experts,
I have a problem with my design as below
ERROR: in SHAPE (-2.3622 2.3622)
class = ETCH subclass = TOP Part of Symbol Def SHAPE_4725X4725. Which is part of a padstack as a SHAPE symbol. ERROR(SPMHDB-187): SHAPE boundary may not cross itself. Error cannot be fixed.Object has first point location at (-2.3622 2.3622).
Can you tell me how to solve my problem?
Thanks a lot.
I would like to be able to copy my fab notes from my database and export as a .txt file.
This way my board house can easily edit the notes to their specifications and hopefully I could import in their modified text file
Dear experts:
We have already designed schematics ,while the component is not standarded,so we need to edit all component porperties for one time.
The way we choose is : export schematic porperties to a document named with *.exp,open with excel,edit all components porperties in excel,then import this exp document。
But when we import exp document,the component porperties updated is B occurence,not A instance.when we copy components,the component just have A instance,not B occurence.
It will make some problems,so we want to repalce instance by occurence.
We try to run ccessories - tran occ prop to instance - push occ prop to instance,it fails,cadence seems always bankrupt or not work,and the schematics can't be opened again.
What is the problem? The way we choose is right? Do you have any advice?
Hello,
I have been trying to give OrCad a try but the installer keeps getting stuck. The progress bar for "Downloading files from server" is all full but it won't continue with the installation.
Thanks for your help!