Is there a setting for automatically naming nets from port names in a hierarchical design? That is, when creating a netlist for Allegro in Capture.
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Capture - Net name from port name
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Orcad Capture Smart Pdf Pin Number Issue
Hi,
I generated a pdf file for the schematic but the pin numbers of a part(D2) are missing in the pdf file. But the pin numbers for other parts(like D1) are correctly shown as expected.
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to undo a delete command
hello
is there a way to undo a delete function?
i always use a delete key on the keyboard when i want to delete an object.
but when i do it, i can not undo the delete.
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zcopy question
hello
is there a way to copy an object to two or more layers at once?
i use a zcopy command to copy an object to a different layer.
but i would like to find out if i can do it not to a single layer but to multiple layers at once.
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how to add mechanical drills or mounting holes to a footprint in allegro 16.6?
How to add some mounting holes (or mechanical holes) on a connector footprint that previous exists, and requiries 2 more holes/drills for fixing connector to the board?
I was trying drawing cercles and looking for "drill" propierty, but I don't find any trick for doing this with Allegro 16.6.
The only thing that I find is "add a pin" but doing this way it doesn't work for me; the update symbol gives me errors as Allegro considers them as real connector pins.
How do you do this type of drills?
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Creating module using allegro 17.4 schematic
Hello,
I am creating a module in Allegro 17.4 PCB editor but as expected there is no connectivity information that can be matched with my existed PCB design.
My understanding is the I need to include the same module in schematic design if yes could you please briefly let me know how to create a module in Allegro 17.4 schematic?
Kind Regards,
Nik
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Delete a Cutout in an existing design
I need help - new to Orcad, I am using PCB Designer 17.2.
I'm working on a PCB design that I inherited from an Evaluation Board. The design had a cutout that I need to remove. I have tried everything from enabling all layers in Colors Dialog, to searching and sub searching the web for anything relating to this.
See attached picture - how can I delete this cutout?
I hope to hell the answer is not something simple, but if it is, my bad.
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Unrouted net
Hi,
Among the components in my layout, I have a transformer and an electrolytic capacitor (see picture).
All the nets are routed, except this one. I've tried to think about everything - but for some reason, Allegro insist to keep them unrouted.
In layer #2 (Power), colored in yellow, there is a shape that covers them both, incluting thermal releif. It seems that they must be routed: both pins and shape in the same net name.
I have also checked the padstack of those 2 pins - both are defined well to all the layers.
At the top layer (green), the transformer pin also connected to SMT capacitors - very well.
What do you think?
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How can I select a pcb layout item (net or pieces of tracks) and deleting it? I'm unable to select some of them.
Hi!
I've opened an old project and after making the translation to 16.6 there appeared two bits of track that belongs to GND net. But the pads belongs to CHBN net. I don't know why the two gnd conductors has brought here. There is no GND pads near the position where they appear.
I named the two bits 1 and 2 with red colours as can be seen:
1 and 2 bits of track are two conductors that I would like to delete but I'm unable to select them, so deleting them too.
When I try to select them, the console launch this msg: Selected item not valid for current operation, ignored: Net "Gnd".
Please can anyone tell me how to proceed to get my target done? How can they be selected? how can it be deleted from here?
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Hug only routing not working
I'm trying to route on an inner layer using bubble routing in hug only mode. Clearance view is set to channel so if I see a gap it should be possible to route through. However, it's not. I cannot route between the holes in the below picture.
If I set Bubble routing to off and simply route through I don't get any DRC errors.
The holes above are 0.2 mm and are 1.0 mm apart. The track is 0.15 mm wide. The grid is 0.1 mm. I have a line to hole clearance of 0.3 mm so I should be able to route between the holes. "Unused via suppression" is, by the way, enabled so the holes belong to vias, that have no annular ring on an inner layer if the via has no connection on the layer.
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Orcad PCB Designer Rats config
Hello
I'm new to Orcad PCB Designer, and i'm sure this problem is easy basic fix, but i can't find it, in any video or post.
For some reason, some of the Rats in one of my PCB's apear with an X in for each connection insted of the classic line conection the points. This appens only for the power signals.
Can this be changed to appear all as lines ?
PS: Version 17.4-2019
Thanks
Pedro Peixoto
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Importing from other tools
I'm having an outside vendor do some layout for us, but they don't have Allegro. The options are: Altium, PADS or Expedition. Which option would import with the fewest problems?
I'm using Allegro 17.2
Thanks
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Error: PXL failed. Unable to package the design.
Hi,
I want to export physical, but appeared "Error: PXL failed. Unable to package the design.".
Could you help to check it? Please refer to attached file "pxl.txt"
Thank you.
community.cadence.com/.../pxl.txt
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OrCAD launch issue 17.4 as custom launch window appears everytime
I am facing this issue in opening OrCAD capture 17.4 s005. When I launch to capture the window appears as shown in attachment which takes about 1-2min stay and later license option appears. Its time consuming and delaying the work whenever I close capture and reopen again. I tried with capture.ini renaming, deleting workspace, installing in different drives yet the issue remains the same.
Any suggestions would be appreciated.
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No logical connections between footprints
Hello everyone.
I have been working on a project and I've come across such issue.
I created a schematic of a power converter. Here's a piece of it. Q1 transistor is in SOIC-8 package (1,2,3 - Source, 4 - Gate, 5-8 Drain).
I assigned footprints and when I imported netlist, I noticed that there are no logical connections between pins (Net number is correct, however). How can that problem be solved?
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how to lock alias in page view
how could i lock a net alias in page view mode ?
when i RMB a net alias , there is a lock option, but it doesnt work.
who can teach me how to lock it , and the tck/tk command ?
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How to handle "unconnected pins" when they are apparently connected throught copper tracks?
I have done a translation from old project to 16.6 orcad version. I have followed the whole of files traslation steps, importation, configurations, etc until I had no errors. I generated netlist and update the board layout. So looking to the pcb editor canvas it can be seen that there are some rastnets between pins that are connected because they have tracks connections. I followed the tracks, vias, etc path and there are electrical path. So I don't know how to solve this.
example:
So I generated the unconnected pin report and this says that there is unconnected some of them, including the one seen at picture. I check the track names and all the segments forming the track path has the same net name.
How can I deal with this? How can I do for looking the part that is not connected? can it be an interface mistake? I'm sure that the two pins has connection has a continuous track connection.
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Is it possible to delete an only one rastnet instead "delete all" in allegro 16.6?
Hi, I've seen that allegro 16.6 there is an option that allows us to delete all rastnets at a time. I'm wondering if it is possible to selecting one rastnet and delete it.
I was trying to select one of them, but when I click "delete" it stills being there.
I have checked "rastnets" on the "find" objects tab.
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Extend Rigid-Flex!!!
Is there any easy way to extend the flexes in a rigid-flex board without rerouting the board and remake the outlines?
I know You can make groups of components/routing and move relative to current position, but how to cope with board outline, keepouts and others?
I´m using Allegro PCB Designer version 17.2
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Increasing distance between traces and planes.
I am trying to increase the distance between planes and traces, and anything I seem to try doesn't work. I have messed with settings in the constraint manager and nothing seems to change in the way I am looking for. Sometimes when messing with settings it seems to create new traces that are narrower than the ones in the picture, below the traces. Any help is appreciated.
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