Hello
Tool version :17.2-2016 S063
When I export step file ,outer layer (Coverlay) thickness is not added to step file (Refer first image) .Showing wrong PCB thickness (0.28mm) on stepfile.
As a workaround i removed outerlayers from cross section and added its height to mid layer (as shown in image2) then I got proper thickness on step file .
Anything I am missing here ?. Please suggest ?
Thanks
Girish
I'm trying to draw tracks from one net pad to other pad/via of the same net (they are connected electrically = rastnets). But when adding connect action, I'm unable of tracing the track making a correct way.
I have seen/read at several tutorials and videos about tracks, that I can create track segments, and then turning left, going stright or turning right by clicking left mousse button after every segment.. until arriving to the target point.
Why I'm unable of doing this? Why is the CAD the path that it wants making a mess in my layout?
It is forcing track paths that are breaking all the design rules, so connecting points that must be unconnected. Even it starts painting at points where there is no electrical connection (pad, pin, via, etc..).
I have this configuration for my current "add connector" action:
I also tried with bubble = OFF.
Is it something wrng? how can I control my track path when painting it from starting point to a second point?
I’m learning with Allegro PCB Designer tutorial. Creating a Shape for the VCC Power Layer, isn’t working as stated. Prior to the operation the DRC flag is Green. Yet, as soon as I complete the following operation the DRC flag turns to Red.
· In mode Etch Edit, no selection
· Shape > Polygon
· Set Active Class ETCH and Subclass VCC
· Set Shape Fill type to Dynamic Copper.
· Browse and select VCC as the assigned NET
· Use mouse to create the polygon on the board
· RMB Done
· Tools > Update DRC
A very straightforward Operation. Yet, as soon as I Update DRC the DRC flag turns to Red. If I run Tools > Quick Reports > Design Rules Check (DRC) Report I get a blank report stating Total DRC errors zero 0. If I run Tools > Quick Reports > Design Rules Net Shorts Check (DRC) Report. I also get a blank report stating Total DRC errors zero 0. If I delete the newly created shape, and re-run Tools > Update DRC the flag return back to Green. I also tried to create that shape on an empty are with no packaged, same result.
Can anyone help me understand what is going on ?
What could be the cause for that strange DRC flag yet no reported DRC error ?
Thanks for your help
I have an interesting problem. I have eight (8) connectors on a PCB. One, for some reason, is giving me problems. I am getting a DRC problem. I have NO IDEA why I am getting this problem. Here is some picture for a better understanding:
I have no idea how to fix this problem. Please provide a STEP BY STEP resolution to fix this. All other connectors are just fine.
Thank you.
JTL
Hello all,
How can I can edit or change the following layer name?
I am self learner of PCB editor. I was trying to design the copy of a file I already have (A reference board file). The above picture is the top layer name of the PCB reference board file. The default layer name for the board I have been working on is simply "TOP". How can I change the class name from "TOP" to "L01_TOP"
Regards,
VT
I have this symbol in a library project that has been created some years ago.
Today I was translating the project to 16.6 starting by updating libs. Then I created the netlist and this process was OK, without any error. When I try to update PCB from netlist the process launches the following error:
ERROR(SPMHNI-196): Symbol 'CONNVMEST64PACACODADO' for device 'DIN 64_AC-H_1_CONNVMEST64PACACO' has extra pin 'X2'.ERROR(SPMHNI-196): Symbol 'CONNVMEST64PACACODADO' for device 'DIN 64_AC-H_1_CONNVMEST64PACACO' has extra pin 'X1'.
The fact is that symbol has no X1 and X2 pins. When I open the fooprint layout I can see how two holes for clamping the connector to the board is considered as two more pins:
I'm sure this two holes were created originally not for being pins connectors neither pads.
How can I access the footprint drill X2 and X1 above in order to say that these holes are not a pins?
Thanks in advance to everyone.
I am currently going through the Allegro PCB Editor Training Manual. Lab 10-4 mention the SPIF interface. In the PCB Editor Help the SPIF command appears. Though I can clearly understand what the SPIF command does, nowhere on the WEB nor Help nor the Training manual is defined what SPIF stand for, at least, I couldn’t find it. Is it an acronym ? If so, what are the words ? Where does the name SPIF come from ?
Schematic NETLIST is generated without any error. I can Import into PCB Editor from Import > Logic with no error. On my Schematic I have a GND Net and a VCC Net as well as many other Nets. The Cross Section is comprised of TOP, GND, VCC, BOTTOM ( 4 layers ). GND layer has been assigned to the GND Net and VCC layer to VCC Net, using the creation of rectangular Shape creation, as directed in the Allegro PCB Editor Training Manual. Placing is complete and no DRC error shows up. I am ready to AutoRoute the board.
Everything goes quite well and the Board is now routed, still no DRC errors shows up.
Yet, I clearly see GND segments on the TOP and BOTTOM layers as well as VCC segments on the TOP and BOTTOM layers. It’s as if the AutoRouter did not observe the VCC Net to VCC plane assignment nor GND Net to GND plane assignment. Net Assignments to Plane where performed without error and Shape colors appeared on the screen after completion, so I have no reason to suspect the assignment went wrong.If I transfer a TOP net segment to BOTTOM where a GND segment is crossing, I get a DRC error clearly showing that both segments are in contact. Which clearly indicate that this GND segment is located on the BOTTOM layer.
What Im I doing wrong ? What can be the source of this problem ?
How to generate the S2P file format from the power SI tool?
Hello, I need to ask a question regarding hierarchy in allegro schematic. I have created one but now i need to make changes to one section so that its not reflected into the other?
Is there a setting for automatically naming nets from port names in a hierarchical design? That is, when creating a netlist for Allegro in Capture.
Here are two screen capture of Before and After Autorouting my board. Padstacks have all been revised and corrected. The Capture Schematic is correct. All Footprints have been verified after Padstack revision. a new NETLIST generation have been done after some corrections made in Capture. I have imported the new Logic. I revised my Layout Cross Section as such: TOP, GND, VCC, BOTTOM. Both VCC and GND shapes have been assigned to their respective logical GND and VCC Nets (verified). Yet, I still have the Autorouter to systematically use extra vias to make GND and VCC connections to the VCC and GND planes. Where a simple utilisation of the part padstack inner layer would have been indicated. What Im I missing ?
Variants seem to be defined as present or not present.
Is there a variant that can assign different parts to the same reference designator? i.e. R17 can be either 0 ohm 0805 jumper or 12k ohms 0805 resistor.
The simplest way I can think of is to use two parts with the same footprint and overlay them.
Is there a more functional way of doing this? So that the variant would put the correct part in the BOM and the parts would of course have the same identical footprint.
Is anyone else using Constraint Manager within Capture? This is my first time using it. I'm finding that it is occasionally changing some of my constraint values in Allegro. It seems random.
Picture 1 show a Shape created in Allegro PCB Editor 16.6, file LTshape.ssm The Shape Origin is dead center of the outline 565X400 mils. This Shape is utilized in the PadStack Editor to create a special Pin for a custom Footprint.
Picture 2 show the PadStack Editor first page with drill size and offset. File LTshape16.pad Picture 3 show the PadStack Editor page 2 with that LTshape utilized as the BEGIN LAYER for copper area. Picture 4 show the actual Package (footprint) finished with Outline, padstacks for pin 1,2,4,5 and that special Pin 3 LTshape. Its origin is also dead center, same as LTshape.ssm
Notice the round dot at the bottom of Pin 3. It only appear in the Package drawing, not in the original Picture 1, the actual LTshape.ssm or LTshape.dra
Picture 5 shows that same Footprint in the final board in PCB Editor. That same dot, now pink, is still there and cannot be selected separately. When using the Find Option and selecting each object separately, the only way to select Pin 3 is when Option > Pin is selected. Then I can hover on the dot near Pin 3 and the whole LTshape lights up as pin 3, but not the pink dot. There is absolutely no way I can select that dot as an object. There is no way to know the existence of that dot except by looking at it. Cannot be deleted, cannot be selected, can only be invisible if I use the Color Visibility manager and disable all 4 layers, TOP GND VCC BOTTOM. If I turn On TOP then the dot becomes pink. With GND On the dot is green, VCC On will get a Red dot, BOTTOM On will not show the dot but Pin 3 turn On since LTshape is the actual Net connected. This Net is not GND nor VCC, it is N357726.
Where is this dot coming from and why is it not a selectable object ? Why can I not delete it ?
I am using PCB Editor v17.2-2016.
I tried to do placement by schematic page but not all pages are displayed.
Earlier, I successfully do the placement by schematic pages and it was showing all the pages. But then I decided to delete all placed components and to do placement again.
When I try to do placement by schematic page again, I noticed that only the pages that I have successfully do all the placement previously are missing.
Hi everyone! I'm working on a small battery powered PCB which will fit inside a small plastic "hockey puck" container. A number of these "pucks" will be sold together with a "charging doc" which will store and charge the pucks when not in use.
I'm trying to work out the best way to charge the battery. I'm thinking of having metal "pads" on the rr.com puck that pass through the puck's plastic shell and then make contact with the PCB on the inside, and having a similar system on the charging dock. I'm thinking of having SMD "contact sprints" mounted to the underside of the PCB and have these mate against metal pins that protrude through the puck, but it's the later of which I'm struggling to find. For a visual, think about "restaurant pagers" and how they charge.
Hi, I am in the middle of a design and had no problem going back and forth between schematics and layout. Now I am getting the error message below. I am using Cadence 17.2.
ERROR: Layout database has probably been reverted to an earlier version than that, which was used in the latest flow or the schematic database was synchronized with another board.
The basecopy file generated by the last back-to-front flow not found.
ERROR: Layout database has probably been reverted to an earlier version than that, which was used in the latest flow or the schematic database was synchronized with another board.
The basecopy file generated by the last back-to-front flow not found.
Error: CMFBC-1: The schematic and the layout constraints were not synchronized as the changes done since the last sync up could not be reconciled. Syncing the current version of the schematic or layout databases with a previous version would result in this issue. The constraint difference report is displayed.
Continuing with "changes-only" processing may result in incorrect constraint updates.
Thanks for your input
Claudia
I've redesigned a custom TO220FLAT Package
First I created a TO220shape.ssm with PCB Editor. Then I created a surface mount T220build.pad in Padstack Editor using TO220shape.ssm. Then I created a TO220FLAT.psm in PCB Editor. I placed 3 Connect pins and 9 Mechanical pins for the TO220 TAB, using standard through-hole pads for better current handling.
Adding those Mechanical pins created many DRC errors caused by the proximity of those pads attached to the TO220shape.
Thru Pin to SMD Pin Spacing (-200.0 0.0) 5 MIL OVERLAP DEFAULT NET SPACING CONSTRAINTS Mechanical Pin "Pad50sq30d" Pin "T220build, 2"
I corrected the situation (so I though) by Waiving those DRC errors, thinking that they could not cause any problem and because that’s what I want, i.e.: 9 through-holes under the TO220 device. The idea being that when this device is mounted flat on the PCB it could carry lots of current via 9 pads that could make a good high current conductor to inner layers.
I then saved the Package and updated all related footprint schematic parts in Capture. Created a new Netlist. Then I imported the new logic into PCB Editor to reflect that change. When the File > Import > Logic is finished I get no feedback error! (which, for me is a substantial achievement in itself)
Now, in the Design Window I see all those DRC errors popping up again, despite the fact that I waived those DRCs back in the Padstack edition. If I run a Design Rule Check (DRC) Report I will see all those DRC listed again. Now, I understand that I can go ahead and waive all those DRCs (100 in total) but I’m thinking there is got to be a better way of doing this.
Please, any advise is welcome. Thanks
