Hello, i'm a student studying Allegro and want to know about auto-routing function.
When the tool routes automatically, is this function grid-based?
If so, how much is the grid size set to this function?
Thank you.
↧
Allegro PCB Designer auto-routing
↧
Orcad Capture CIS - Footprint viewer problem
Hello
I am using Oracd capture CIS from longtime and it was working fine till 16.x version.In 17.2 onward I am unable to view footprints on capture CIS window
I explained my problem in the below image, If anyone come across the same issue and got resolved ,please help me .
I did detail check on the flow cad PDF (https://www.flowcad.de/AN/FlowCAD_AN_Capture_CIS_Environment.pdf) for the right setting but unable to figure it out the actual issue ?
Regards,
Girish Kumar
↧
↧
Mounting hole with vias to ground
I have been trying to design a mounting hole with vias around it which short the pin to GND.
So far, I've created a padstack of the main mounting hole and a via as a Thru-Pin element. I want to add the vias around the mounting holes but I've been getting DRC errors.
The final footprint is being created as a Package Symbol. How can I fix it?
↧
Trim Silkscreen Outside Edge of Board
Hello
Is there any way to trim the silkscreen outside the edge of the outline? I am using the SILKSCREEN_TOP subclass. Thank you.
↧
Warning possible pin type conflict GND
Newbie question here :
I get way too much warnings about "Possible pin type conflict GND".
Many tied to IC GND power Type pin.
In the ERC Matrix, Power to Power shouldn't report any warnings...
↧
↧
How to add solder mask to teardrops ?
Hey guys , when i was making a keyboard pcb , i found this images.
this is a pcb of keyboard too . what interested me is that all of it's clines , thr-pins , vias and teardrops are added solder masks , and shows out an open-windowed , blackgold effect , and i think i want this visual effects too .
then i tried it in allegro . first i export a sub_drawing file out of the pcb , selecting the clines and vias before picking the origin spot , and a .clp file is there in the folder where the pcb .brd file is . Then i open the clp file with the vscode , and replaced all of the "etch/top" and "etch/bottom" with ''Board_geometry/soldermask_top'' and ''Board_geometry/soldermask_bottom '' . then , i import the modified clp file into the pcb , and this help to add a mask layer to the clines and vias . in the 3d viewer it is like this
it shows the same effect in the first image i posed , the clines , vias are added soldermask .
but i can not achieved the effect in the second image , cause i don't know how to add soldermask to the teardrops . when i exported the subdrawing file , i can only select the clines vias pins but not the teardrop .
Anybody knows know to add soldermask to the teardrops can give me some ideas ?
↧
License requirements for Ultralibrarian and Samacsys for usage in OrCAD
Do we need any license for the ultra librarian and Samacsys to use within OrCAD tool
I am using OrCAD Capture 17.4 with the latest hotfix.
↧
Unable to click OK button under Setup - User preferences, as tabs going beyond screen resolution
I am using OrCAD PCB Professional and recently update with the hotfix. With the latest hotfix installed I am facing issues in selecting OK tabs under setup - user preferences.
I cannot update any .pad path, .psm path, or any features selected under User preferences as I am unable to hit on the OK button.
I tried varying screen resolution yet the issue remains the same.
Any help would be appreciated.
↧
17.4 - HF007 - Disable Capture StartPage...
Previously, there was a way to disable the startpage by adding
[Start Page]
EnableStartPage=False
in the file spinfo.ini but in spite of this the start page is displayed in HF007. Any other way to disable it now?
↧
↧
ERROR(ORPSIM-16366): Line too long. Limit is 245 characters
Hi,
I try to use EPC PSpice (.net) model (epc-co.com/.../EPC2035_V2_PSPICE.net) to my simple circuit. After saving the .net file to .txt then .lib, getting .olb file from model editor, adding the .lib file to Configuration Files/Library. The following problem appears during runtime. I tried to break longer lines in the .lib file (in fact no one line is too long) with +, and also tried to use \ at the end of line in stead of + at the beginning based on some suggestions. The problem is always there.
* (C) Copyright Efficient Power Conversion Corporation. All rights reserved.****************************************************************************** Version History:* 1.00: 04/20/2015 - Initial Model Creation* 1.01: 02/19/2019 - Updated t
* 1.02: 02/26/2019 - Added a missing parameter
.subckt EPC2035 gatein drainin sourcein .param aWg=159 A1=5.5332 k2=2.2219 k3=0.15 rpara=0.025065 rpara_s_factor=0.29 + aITc=0.004104 arTc=-0.0054 k2Tc=0.0006 x0_0=1.5473 x0_1=1.0199e-06 x0_0_TC=0 x0_1_TC=0 + dgs1=4.3e-07 dgs2=2.6e-13 dgs3=0.8
$
ERROR(ORPSIM-16366): Line too long. Limit is 245 characters.
Index has 0 entries from 1 file(s).
ERROR(ORPSIM-15108): Subcircuit EPC2035 used by X_U1 is undefined
Thank you in advance!
↧
how to copy or duplicate a schematic page?
Hi,
In my design I have a schematic page that I'd like to use as a basis for another page in the same design. In the manuals I cannot find a description of how to get two copies of this page in the design. I have poked around in the tool and can't a way either.
I am using allegro design entry hdl.
Thank you.
↧
Just switched from OrCad ver 16 to Cadence/OrCad ver 17
Long time user of OrCad capture and layout ending with ver 16.2. Now I have the ver 17.2 Capture and Allegro PCB. Really not intuitive so could someone point me to the proper user manual to cover copper pour/fill details. I translated my layout .max file and the bottom plane is a combination route and ground plane created with a pour/fill. After translation I see only the routes and would like to see everything, which would include the pour.
Does a Tutorial, like that found in ver 16.2, exist? The 16.2 Tutorial was a very nice reference.
Please do not criticize my verbal use of 'fill', intermixed with 'pour', as I also have to work with PADs and it causes me confusion.
Looking forward to a reply.
Thank you.
Jaye
↧
Creo Parametric 3.0
Has anyone seen copper artwork successfully imported in Creo Parametric? I've seen it done in a Youtube video, so I know it's possible. I've created an .eda file using Creo View, but all we were able to import is vias. We do have the ECAD/MCAD collaboration license.
↧
↧
What causes BoardOutline/Cutouts to not show in the 3D canvas?
Not finding help on diagnosing this on CDNS website. Just me? B-)
What typically causes this?
↧
Some pages of Allegro PCB 17.2 is freeze under Win10 2020.
My computer was updated by Microsoft automatically last week. Before Win10 2020 was updtated , Allegro PCB was run normally. After updating, some errors was appeared.For example, The Define Grid page of Design Parameter Editor is freeze when i will want to modify Grid data value under the circumstances which clicked Design Parameter Editor in Setup menu and clicked Setup Grids to modify grid value. In other words, when i clicked Setup menu of allegro PCB and clicked Design Parameter Editor item, in the page, i tried to modify grids value of Setup Grids page, i will get nothing on the Setup Grids page. Setup Grids page will be freezed. And i can not close the Setup Grids page as well as other pages.
By contrast, if i clicked Grids item of Setup Menu of Allegro PCB , the software will run with no errors as well as modify the grid value sucessfully.
The Second phenomenon, the Setup text size page of Design Parameter Editor item in Setup menu was clicked and i can not be modified any value too. The cause is as same as Setup Grids page. The allegro PCB was freeze too.
Who know how to solve it? My Computer os is Win10 2020.
↧
Blind And Buried Via Overlap
Hai,
Is there any way to find the overlapped blind and buried via. if it possible can anyone please guide me how to do it.
↧
OrCAD EDM vault and key requirements for a team
We are a team of five working a complex project. To keep data integrity and the version control we are moving to EDM but, we are in an unclear mode regarding how many licenses would we need.
So for the team of 5, whether we need 5 OrCAD EDM key license and 1 OrCAD EDM Vault or 4 OrCAD EDM Key and 1 OrCAD EDM Vault.
It would be more useful if you can add more info on how EDM vault and Key work combined.
↧
↧
search providers not working
Hi Since I download and installed service pack S007 in orcad 17.4-2019 i cant get the search providers to work
after a while this error message pops up
{"errorType":"Service Unavailable","errorCode":"SPDWSRV-000111","errorDescription":"ERROR (SPDWSRV-000111): One or more services are not available because the server is in maintenance mode."}
Has anyone else seen this error.
↧
DRC checks for covers
Most of our designs are RF and we require channelized metal cover for isolation. More than once we've had via shorting issues due to either overlooking it or last minute changes. I'd like to be able to setup constraints for a DXF layer that represents the cover to any copper that's hot (any net other than ground/return). Is this possible? I'm using Cadence 17.2 PCB Designer. No other add-ons
Thanks
↧
TCL - Get the Most Recent Part
I'm using the PlaceNew tcl procedure OrCAD Capture to have the user place a new part. I would like to be able to get the part instance that was most recently placed on the page and can't find a very good way to do this.
The best solution I have so far is getting the most recent mouse click and selecting a small box at that point and choosing the first object there but this is not ideal.
I thought I might be able to iterate through all parts on a page but the last part in the iterator does not seem to be the most recent part. Also sorting parts by ID or name doesn't seem to guarantee chronological order either.
Has anyone seen a way to do this?
Thanks
↧