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Skipping pins in footprint only

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If I need to delete the even numbered pins in a footprint while leaving the schematic symbol unchanged, how would I do that?

I have a high voltage application with large copper clearances, and I need to use an existing connector.  To get the clearances, I need to remove every other pin.

What I think I need is to replace each even numbered padstack with one with zero copper and zero through-hole diameter.  Does a dummy padstack like this already exist?

When I just edit the footprint (.dra) to delete pins, I get netlist errors because the footprint no longer matches the schematic symbol (obviously).

I'm using OrCAD 17.2 PCB Editor

Thanks


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License error after system crash

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At the moment I'm working in home office with a VPN to my companies license server.

Sometimes the VPN is unstable and I loose the connection the license server. So I have to close my PCB Designer.

After reestablishing the VPN and restarting the PCB Designer it tells me that my license is already in use.

Of course I have no access to restart the license server. So is there any way to reset my license?

PCB Keepout for pad

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I am using OrCAD PCB Designer Standard 17.2. I am routing a power line through between 2 narrow pins, like this:

I want to route the line like this, how should I do?

The idea is to create a PCB keepout for these 2 pins and a route for the line to go straight, but I don't know how to do it. Please help me. Thank you very much.

Creating and editing models

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Hi Friends

I needed an LM565 to simulate, but unfortunately, the software did not have that LM565, and I accidentally saw this code on the Internet!
But I do not know how to give this code to the software!

The code is available in the following file

community.cadence.com/.../6013.SUBCIRCUIT.pdf

I have another problem and that I do not know what the format code is ?! And that when I copied this code from this PDF I had to change it. Can you help me and tell me if the code in the file above is the same as the code I wrote below or not ?!

Thank You

code:

.SUBCKT LM565 1 2 3 4 5 6 7 8 9 10
C_C1 0 init 1u
R_R3 $N_0001 6 1.75k
R_R4 0 init 1g
R_R6 8 9 10g
R_R2 3 0 10g
R_R1 $N_0002 7 3.6k
E_E15 $N_0002 0 VALUE { V($N_0003, 0)+V(6,0) }
E_E1 $N_0003 0 TABLE { 0.68*V(2, 0)*V(5,0) } + ( (-0.68,-0.68) (0.68,0.68) )
G_G1 init 0 VALUE { (V(7,0)-V(6,0))*0.00001458/(R0*C0*(V(10,0)-V(1,0))) }
E_E13 4 0 VALUE {sin(6.28*(0.27/(R0*C0))*(time+(R0*C0/(6.28*0.27))*V(0,init))) }
E_E3 $N_0001 0 VALUE {0.126354*(0.7+V(1,0))+0.873646*V(10,0) }
.ENDS

Drill file alinment 17.2

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drill file view

Drill file and other artwork files are not alined as you can see in the screenshot. Pink color dots are drill files and other is the bottom layer. I am using cadence orcad 17.2 version. I do not understand the reason for this. If anyone can help, much appreciated.

Mouse Looses Ability to Select Objects in Capture

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Hi,

Strange behavior today. Working on a schematic in OrCAD Capture 17.4 when all of a sudden, I can no longer select any schematic object. I can markee around the object to select it and right click to edit the properties, but loose my ability to left click on anything within the OrCAD schematic. However, by closing everything down and restarting OrCAD, I get my mouse pointer operation returned to me.  I had this issue as well with versions 16.2 and 17.2 as well.  Fixed it doing the same thing...shutting down Capture and restarting and things come back to normal.

This does happen every now and then and only with OrCAD Capture, not with any other program on my computer including other Cadence tools.

Mouse is new and was replaced, so not that piece of hardware.

My Machine:  Windows 10 Professional (64-bit), Dual Xeon CPU with 192 GB DDR4 RAM, 6 USB 3.0 ports (mouse in one), Nvidia P1000 Graphics Card.

Anybody know anything about this problem?

Thanks ahead of time...

Chris


Some holes don't show up in .DRL artwork

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Hi,

I've just completed a design in PCB Designer 17.4 that when viewed using gerbv is flawless except for the fact that four through-holes won't show up in the .drl artwork, each corresponding to one of four pins on the same connector. These pins are connected to a ground plane on layer 2 (four layer board) and all other through holes on the board are displayed normally--even two holes on the same connector that aren't associated with these four pins. I've inspected the pad and it correctly shows oblong slotted holes on each pin. What gives?

Thanks,

John

Report showing net , physical class name.

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I want to generate a report with net-name , physical class , and group class.

I can get the group glass but cannot physical class. 

Is that possible  ? 

I created a drawing, How do I mirror it?

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I am using OrCAD PCB Designer Standard 17.4. How do I mirror it for review\assembly purposes?

Uninstalling Cadence

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HI,

I am trying to understand what happened when I uninstalled cadence to do a fresh install.

My libraries where not in the cadence install folder but siting on a onedrive folder remote from anything cadence, the only reference to the libraries was in the user preference paths, but uninstall seemed to have found them and deleted them without warning.

Is this what happens, you cannot uninstall without losing everything?

I was lucky that I was able to get the libraries back from my remote backup, but it could have been a disaster

Jessica

Flex zone slide arc

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Since you can only use the shape edit to edit a flex zone shape, how do you slide an ARC ? Or change the ARC to a right angle  ? 

Export Constraints from PCB Designer to Capture

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Hi

I have designed a board and added some constraints in the schematic. We've passed the design on to an external layouter and he added some missing differential pairs. What is now the correct way to export the new constraints from the board file back into the DSN. I don't want to import any other changes, just the constraints.

Converting Via into DXF marked circle

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I received DXF file from mechanical team. In DXF has some circle. I have to place via in that circle location.  Is there is any way to place via automatically  in the provided circle location.


How much are various signal protocols affected by PCB design?

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I mostly work with low speed digital signals so I didn't have any problems yet, but just became curious.

How was your experience with various connections like SPI, SWD, JTAG when it comes to PCB routing? How sensitive were they? Do you have any rules or tips to share?

17.4 downrev files

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Hello all,

      we generate the board with editor 17.4 but from customer end to see the board in 17.2 version is there any possible way let me know. even have tried compatible mode of 17.2.

thanks in advance

Error while creating gerber files

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Hello everyone.

I've created a layout and I want to generate gerber files, but when I try to Create Artwork, I receive such error

Database has errors; artwork generation cancelled. Please run dbdoctor

I've checked that the error applies to the logo placed on the silkscreen. How can I approach that problem?

ERROR: in ARC SEGMENT center = (-113.118 2.774)
class = PACKAGE GEOMETRY
subclass = SILKSCREEN_TOP
Part of Symbol Def LOGO_18X10MM_SILKSCREEN.
ERROR(SPMHUT-144): Illegal arc specification.

0 warnings, 1 errors detected, 0 errors could be fixed.

Views background color. Orcad PCB Designer 17.4-S012

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Hello everybody,

is any way to change the background colors for different views. Example:

for TOP view - black

SST+SMTview - white

and so on.

If the background is changed, the color is assigned to all views. How is possible to separate it?

Thanks

Design Padstack on wrong layer / bonding

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Cadence 17.2.

I'm using a library BB-via defined with only one layer (Layer = BONDS, just below TOP) and this is a connect pin of a part.

NB : I'm using this trick 'cos I can't use the Allegro Bonding feature since it is limited to 100 bonds with the std Allegro PCB editor package.


type: Blind/Buried Via
Hole data size = 0.0000

Design layer pads

Layer: BEGIN LAYER = DEFAULT INTERNAL  = END LAYER  = ADJACENT LAYER  = None

Pad

Geometry

Width

Height

X offset

Y offset

Regular

None

Thermal

None

Anti

None

Keep Out

None

Layer: BONDS

Pad

Geometry

Width

Height

X offset

Y offset

Regular

Square

0.0850

0.0850

0.0000

0.0000

Thermal

None

Anti

None

Keep Out

None

In the package, info on pin is correctly defined on BONDS layer.

info on pin:

pin number: 120

Padstack name:   BP_SQR_0-085
Usage:           Bbvia  
padstack defined only on BONDS

When I put the part in the PCB design, the pad is swapped onto the BOTTOM layer ????

info on pin:

  pin number: U1.120

  pin name:     BANDGAP
  pinuse:       UNSPEC
  Zone name:    PCB_P1
  location-xy:  (64.5250 43.1875) 
  Part of net:       N473817_HALF-SIDE0_ADC
  Number of connections: 0
  Reference padstack name:   BP_SQR_0-085
  Usage:           Bbvia  
  padstack defined only on BOTTOM
  pin is EXPLODED from symbol
  padstack rotation:   270.000  degrees
  Attached text:
   class      = PACKAGE GEOMETRY
   subclass   = PIN_NUMBER
   value      = 120

Properties attached to symbol pin

    CLIP_DRAWING      = CLIP_1
 

When I edit this padstack design, the padstack is correctly defined on BONDS layer, as in the library padstack put in the part.

=> there is clearly an issue there.

I did several trials withiout any success:

- db check

- delete part, repackaging, replace part

- update symbol, with and w/o 'Update symbol padstacks from library'

NB : I'm using also the Flex zones, but BONDS layer is enabled on the zone I place this part.

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