Hi All
I tried to generate cusomized report refer to "Extract UI" window with text editor...
but there is no any "find" function so it's hard to find the code that I want.
so is there any document or datasheet to easy to find the parameters?
regard
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document of entire parameter for generating reports
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DRC Driven Same Net Spacing Clearance Working for Through Pins but Not SMD Pins
As stated in the title, DRC driven clearance appears not to work for SMD pins, but does work for through-pins. I can add properties for clearance and type to the SMD pin and that will work just fine, but relying on the constraint and global parameters just results in a full contact connect. I've looked through global parameters and constraint manager and everything looks correct to me, and is the same for both through and SMD pins. Is there somewhere else I should be looking?
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Pdf out parameters
Hi, I have started getting the name of the film as a header and footer in all of my pdfs. The command also writes a pdf_out_config.txt file.
Does anyone know how to configure pdf out to stop this ?
Thanks,
Jim O'Mahony
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Cadence Download manager doesn't complete the install process
HI All, I hope someone may have run into the issue I'm having with the download manager.
The Product installation guide says that the download manager should automatically begin installation of the software after the download process is complete. It does complete the download but then it just stops there.
It never gets to the point where it shows the license agreement page so that I can accept it and move on to the rest of installation.
Does anyone have any suggestions as to what I can do to troubleshoot this problem? The download manager does not seem to have any other settings or controls that I can access to see what might be holding it up.
I've also searched the forum and I haven't found any other posts regarding this problem.
Software:
Cadence Orcad and Allegro 17.4-2019
Orcad and Allegro Products 17.20.0
HDL-Pspice Library 17.20.0
HDL-Pspice Library 17.4.0
System:
Windows 10, 64 Bit
Intel Cor i7-10700 CPU
32GB Ram
1 TB SSD 640GB available
Thank you.
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generate reports which have two more other properties with text edior
Hi All
How to generate report which include two more properties with text editor?
I refer to this "">community.cadence.com/.../extracting-layout-data"
and I follow the the sample code but It was not work well
report only import the first parameter before END
regards
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Mechanical hole
Hello,
I would like to create a mechanical hole in Padstack Editor. This hole will not be electrically connected at all, it just serves as a guide for a socket.
What do I have to put in design layers for the different pads as there is no annular ring on this hole ? Should I put the same diameter for the pad as for the drill diameter ?
Kind regards
Loïc
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Remove designated pad's thermal relief void to copper plane
In OrCAD PCB editor (version 17+), how to remove designated component pad's thermal relief void to the copper plane, so the pad will have a direct connection to the plane?
This should be done only to specific designated pads, while the other pads in the design should keep their original thermal relief behavior.
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Cannot load symbol
Hello,
i completed a schematic design in OrCad Capture and i wanted to create a new layout of the circuit at pcb editor. My circuit consists of some capacitors,resistors,inductors and the IRF150 transistor.The problem is that all components can be placed at the design in pcb editor except for the IRF150 and when i try to place it command window gives the message : " Cannot load symbol '806' ". Could anyone help on this?
Thank you.
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Unable to route
Hello,
I have a rather big issue when I want to connect the components of my pcb. I suspect however that it is simply because I do not know how to use the software well yet..
First, I created two custom package symbols with PCB editor.
Second, I created a board (.brd) file in which I placed my two customs package symbols. The problem is that I am not able to connect the different pins of my packages. When I try to use the "add connect" feature, I begin the trace on one pin but I cannot connect anywhere else, I always have a DRC error saying that I am too close to a pad (which is what I want in order to connect).
Is it because I placed the package directly without begining by a schematic in capture ? Is the schematic mandatory ?
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I also have another question concerning components placements. When I place a component, it automatically adds a boundary in the Place_Bound_Top layer. The problem is that I want to place a component inside another one. To be more precise, I have a ring of plated through hole and inside that ring I would like to place another component. And when I place the second component, a DRC error shows up. Is there a way to disable the automatic boundary when placing components ?
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Last question : is there a way to modify the package symbol and then update the brd file or do I have do delete and replace the modified component everytime ?
Thanks a lot in advance !
Loïc
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Pin numbering
Hello,
Sorry, I have the impression that I ask a lot of questions these days. ^^'
I have two questions concerning pin numbering :
1) In a package symbol, I have two mechanical holes. These mechanical holes have a pin number. Is it mandatory to have a pin number for mechanical holes ? It's just a hole for guiding the plastic part of the component and I don't want to have a pin for these holes in the schematic in Capture.
2) Is it mandatory to have the same number of pins on the schemtic than on the footprint ? The reason is that I have a schematic that have a lot of relays. For readability purposes, I draw the relay symbol as a simple switch with two pins but in fact the footprint has 4 pins (2 pins for the coil of course). Do I have to have 4 pins in my schematic or is there a workaround ?
Thanks a lot in advance
Loïc
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End to end process of schematic capture and pcb layout.
Hi all,
My boss ask to provide him an End to end process of schematic capture and pcb layout.
I just wonder if any of you ever create a document like this? Please share your thought.
Thank so much.
Regards,
TiBo
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Why does my layer name change in XSection when importing a netlist from OrCAD to PCB Designer
Hi
I just stumbled across a strange behaviour. I have a design where I know that the names of the layers had an error (typo) a long time ago (say, July 2020). We fixed that in august 2020 in the PCB Designer. Now we're redesigning the board, have made some changes in the schematic and created a new netlist. When I now import the netlist, the layer name will revert to the faulty one from July 2020.
Why is that and how can I ensure that this doesn't happen? I don't quite see why a layer name should be transferred from schematic to PCB.
My current version is 17.4-2019 S016.
Regards,
Thomas
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Allegro - Check for symbols with changed definition
Hi
I'd like to know if there is an automated way to see if a PCB only uses the latest symbols. Assume that a symbol is created, then placed on the PCB (let's name it PCB-A). A few months later, an error is discovered during another project (PCB-B) and the symbol is corrected. Again, a few months later we're back at working on PCB-A and now I'd like to check if there have been any changes in the symbol definitions in the meanwhile.
I understand that I could simply run Update Symbols for all packages but I'd like to see if there have been changes first (I also don't mind if this would be shown after the update) but I'd like to clearly see which were changed and which not.
Kind regards
Thomas
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In Find by name more pop ups is not working
Hi,
I am using allegro physical free viewer 17.2.
I am facing a strange issue last couple of weeks, in the Find by name option more pop is not coming.
Please help me to resolve this issue.
I have uninstalled the software and tried the issue is not solved.
Regards
Manumohan
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Error in MNL File
Dear Sir,
Greetings for the days...!!!
When i load MNL using Auto ECo mode at that time i got below error.
ERROR: Electrical package PORT4 for comp MA has 6 pins,
but footprint CT5A NEW has only 2 pins.
I Stucked in this problem.
I double checked for all components and its foot print but i am not success to solve so i write here.
please suggest solution.
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Padstack Editor 17.4 problem : Value must be greater than 0
Hello !
I have a big problem when creating a padstack using the Padstack Editor 17.4
In the "drill" tab, I cannot enter any numeric data without having the error message: "Value must be greater than 0"
This problem does not appear in version 17.2 padstack editor
For SMD pad, I have the same problem in configuring the dimensions.
My Cadence version is up to date
Anyone have a solution?
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Capture and PCB libraries files format (olb, dra, psm)
Hello all,
Parts preview in Orcad Capture and PCB designer are all but not user-friendly. Icons are way too small for preview.
Does anyone know where can I find capture (OLB) and pcb layout (DRA/PSM/PAD) files descriptions? I want to start making application for libraries preview. Does anyone know for Python/C/C++ demo application preview for Orcad libraries?
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Adding and deleting OffPages in TCL
I am trying to replace OffPages in Capture with TCL.
I only want to replace specific OffPages and can't use the "Replace Cache" Function
To create a new OffPage I use the NewOffPageConnector on the active page:
$lPage NewOffPageConnector $lStatus $lCname $lOffPage $lLoc
Then I remove the old OffPage with DeleteOffPageConnector
$lPage DeleteOffPageConnector $lObj
As soon as I change the view (zoom, scroll), Capture crashes.
What am I doing wrong?
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Allegro "Update Symbols" disbands some module groups
I have a design that uses two modules (.mdd). When i need to make an edit, i open the .mdd file and make the changes. I save, exit and re-open the main project brd file. At this point i can Place->Update Symbols and select the module name to refresh. However sometimes there is strange behavior, that is one of my modules frequently gets disbanded in the process.
There seems to be a pattern, which is: it's always the same replica that get disbanded every time i try it. and also it works the first time i refresh after a the module is made from "place replica apply". In other words, here are the steps i follow:
1) select my symbols
2) Place replica apply
3) Now i open the .mdd and move a via for example.
4) Back to the main brd file i Place->Update Symbols
5) Select the module name and click refresh
6) All is good, both copies of the module update and i see the change.
7) With nothing else in between, i do Place->Update Symbols and refresh the same module again
8) Now just one of the module gets disbanded.
It seems like a bug to me, how i can i click refresh update symbols once and everything works, then click it again and see groups get disbanded?
I am running the latest hotfix that is 17.20.076 from May 2021. Running on Windows 10.
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Allegro Module Mapping for Parallel components
I'm wondering if these is a way to help the allergo "Place Replicate Apply" determine which components should be mapped for those in parallel.
The common example is capacitors, and although this doesn't create an electrical issue or problem, it's a bit aggravating for someone trying to keep refdes mapping consistent between pages.
Maybe an simple example:
My schematic are laid out in a way that has 4 parallel capacitors on two pages
Page 1: C10, C11, C12, C13
Page 2: C20, C21, C22, C23
Now let's say i layout and make a module of the 4 caps on page 1. I want to create a replicate of the 4 caps on page 2 to map such that
C10 -> C20
C11 -> C21
C12 -> C22
C13 -> C23
However every time i replicate the mapping is random, sometimes Allegro guesses a couple the way i want:
C10 -> C20
C11 -> C21
C12 -> C23
C13 -> C22
Other times it's gets none the way i want:
C10 -> C23
C11 -> C22
C12 -> C21
C13 -> C20
Of course i can do the manually mapping myself and for small modules like this example it's no issue. But for larger modules as i'm doing this is taking too much time. Is there a way, maybe some property, that can be set to pre-map components or help it guess better?
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