I am trying to work on a design Iand I have a lot of 'Line to Same Net' DRC errors and when I check, the line appears to be disconnected from the pad!
If I slide the 'Cline segs', the cline slides along the rest of the line but stays unconnected to the actual pad it is supposed to be connected to and changes to a rats nest????
Hi all,
I've run into a pretty weird problem/feature(?). I've made a symbol for Wurth's 9774060360 steel spacer, and as per the datasheet, the symbol is comprised of one pad, with a non-plated mechanical hole padstack (I've chosen mechanical hole because I want it to be non-plated), and a circular copper pad only on the top layer. The summary of the padstack I've attached as as a PDF.
Now, the strange part. When I use this symbol in a PCB design, it would seem that there are no constraints applied, and no errors given when I try to route traces through (!!!) the symbol on layers where there are no pads defined. This would mean that I can route traces, pour shapes on an area that will afterwards get drilled out! Well, this gets my on my toes a bit. Attached is a picture of what I mean:
This is a 4-layer design, with the top layer in green, third layer in grey and bottom layer in yellow. I didn't show layer 2 because it only has a ground plane (which also goes through the hole!). As it can be seen, those two traces pass right through the hole on Layer 3 and the bottom layer! I've enabled the "Hole To" constraints in the Spacing constraints configuration window in Constraints Modes, but I'm still able to do this.
What's going on? I would have imagined that violations like these would raise all kinds of DRC errors, but it would seem that this is something that I can easily do.
I'm using OrCAD PCB Designed Professional 17.2 with Hotfix S076 installed.
community.cadence.com/.../c740hn440m750zc0xc0mx450.pdf
My Allegro .brd was originally done in 17.2. We moved to 17.4, engineer made changes that somehow wrecked some trace width constraints. When I open CM and try to correct them, I get this message:
All I need to change is the 0.0820 to 0.0890 and I don't understand the message. Yes, I've tried the max width first, but still get the same message.
Any feedback would be greatly appreciated.
Thanks.
Alexis
When i open the "Update Symbols" window, and expand the dropbox for the "Place replicate modules", it contains a list of modules, new and old, and many no longer exist in my working directory. Is there a way to refresh or update this list? The list is getting long and cluttered and the majority no longer exist since i deleted them.
Will you, please, direct me to the correct forum (or web page) for the following technical help?
Situation:
1) I have ORCAD/Allegro 17.2
2) Digi-Key almost always has Allegro 17.2 foot prints for what I want but not always the symbols.
3) I do not know how to make the ORCAD symbols and then "connect" to the foot prints furnished by Digi-Key.
Will you please point to simpleton's "How To" video or step by step description?
John
Hi All
I got the brd file from other designer but some footprints omitted the Silkscreen data.
so I exported the libraries (pad, psm, dra) to add the Silkscreen data at current directory (.)
even though I modifed footprint data and refreshed, but the silkscreen was not added...
do I need to edit the path or some setting value?
regard
I updated line to line spacing constraint value in the constraint manager, and the “Actual value” is already larger than “Constraint value”, in other words it is obviously meeting the requirement of the constraint, but I am still seeing the DRC, see below on the two lines, constraint value is 5mil and actual value is 7.08mil.
when I "display DRC", I see the same thing, "Actual" value (7.08mil) is larger than the "Required" value (5mil)
It is obvious the actual layout is not violating the DRC, but why am I still getting the DRC?
This is not limited to line to line spacing, this happens on other spacing constraints as well, i.e. having actual value meeting the constraints but still getting the DRC.
How can I resolve this issue? and not by waiving he DRC as I have too many of these to waive one by one.
Thank you.
Hey guys
I was working on a test point to component csv parser file to see if I could find test points that were too close to each other according some clearance rules and the scope expanded beyond what i'm capable of right now on the software side of things. While still working on this project for my own sake, I wanted to know if there was already a feature of OrCAD PCB Designer where I could see a report of test points that are too close to components or that would at least display distances between components, if they're on the top or bottom. I would like the edge to edge distances between the test points and components.
Hi,
In my design, all the properties are updated in occurrence (the properties in the instance is different , the design is flat design). I wanted to copy all the occurrence properties to instance properties. But when I try to push the occurrence to instance, all the instance properties are getting copied to occurrence. (used option Accessories> Transfer Occ. prop, to instances > Push Occ. prop, to instances)
Can anyone help to solve this issue?
I have tried in Orcad capture 16.6 version and Orcad PCB editor 17.2 version also
I try to place the capacitors parallel but the wires are weird.please see the picture below. The problem is gone if two capacitors are apart more than 200 mil or misalign. I tried to change the footprint and check the constrain but no help. How can I solve the problem? 
Exported pdf file from Allegro - OrCAD 17.4
Expected PDF file something like this (I have used GC-Prevue Gerber viewer tool)
Thanks
Hi everyone,
i have two variant in project which is done in capture CIS 17.2. if select any one one of variant Variant name is not update (Marked in red color) two variants are in Green color
In Variant Name it should be AC version or DC version. but it is not updated. version are updated in all the pages if i select any variant but it is not updated in main page. Can any help for this post
Thanks
kabalee
I am trying to move a component that I placed but the symbol now has random vias and traces attached as part of the symbol. How do I remove the association?
I'm editing an existing layout and the SI engineer has defined the targets for DDRs as the _T and _C pairs in each group. The previous designer made the pairs as short as possible and then added length to the rest of the sigs in the group. In this case, the other lines in each are way too long and I can't make them shorter. On the previous design, the pairs were never lengthened, so my question is: Will it be OK for me to just lengthen the pairs so the rest will be more easily matched? The SI guy is in another time zone and I didn't really want to wait a day for his response. Hoping to get a sanity check from the Community. Thank you.
Hi All
I use 16.6 latest hotfix like below
when I hit the CM rule button OrCAD PCB program suddenly down without any error message or log
it seems like bug
How can I resolve this bug? I installed 17.2 and 17.4 version FYI
regard
Hi all
I set the 0.2mm of SMD pin to BB via at the samce Net spacing rule
and I tested like below. each couple of left one is SMD pin and right one is BBvia
I set the 0.2mm spacing. so left column set occurring DRC error is correct.
but when the SMD pin is coverd by BBvia over half, DRC error was not occur as you can see the right column set
but if BBvia take apart from center of the SMD pin, the DRC error occurred again, before then DRC error was not happened..
How can I handle the that DRC error marker without waive DRC?
I don't want to occur DRC marker when SMD pin and BBvia are contacted even slightly
but if they are apart, same net spacing Rule must be effected.
(pin and via are located same layer)
reagard
Can anyone help me set up a hot key to route from target?
Hello,
I would like to import my company logo on my PCB. I manage to do it but the letters are not filled.
Is there a way to to fill it ?
Loïc
hellow,
I find the copper residual rate using metal usage or film area. (tools-metal usage , tools-quick reports-film area)
But, The results of the two methods are different.
So I wonder about the logic that both methods calculate the residual rate.
If anyone knows, please reply.
I wonder what the film area short report is.
Metal Usage Report
-> Calculate metal residue of layer
-> The Metal Usage Report accurately assesses the percentage of metal in a specified region of the design
Film Area Report
The metal percentage calculation takes place as follows:
-> If the board outline is added as a shape then the metal percentage is calculated between copper and board outline.
-> If the board outline is drawn with lines then the metal percentage is calculated between copper and route keep-in. However, if the route keep-in is not defined, metal percentage is not reported.
I'm a beginner using Allegro and have a few basic questions related to placing parts. I'm trying to place a connector in a specific location relative to something else and have had some struggles with placement. Is there a simple way to place something a a specific location? I've resorted to drawing rectangles and snapping them to other objects and drawing them to size to give me another snap location but it seems like there should be an easier way. Though I've been able to place the parts I still end up being one or two thousandths of an inch off what I really want it to be. Similarly, is there a way to draw just a line of specific length? The reason I've been using rectangles is because I cant find a way to draw a line and dictate its length like I would in a mechanical CAD program. Finally, when moving parts I know I can use the Find Filter to grab components by specific pin numbers and specify the pin number, but I still cant seem to actually grab the pin.
Any help appreciated.