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Expanding status bar in Allegro 16.3/16.5

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 Hi everyone,

 I have a question need your helps, much appriciated with your suggestions.

The net naming in my design is too long so that does't fit in Status Bar (please refer attached picture). So, is there any way to expand the Status Bar (particually in Net name) inorder to fit in long net name ?.

 

(I probaly know other ways to see the net name by showing Element or Property Tab)

 

Thank you,

Have a good day all.

 


Amazing problem while generating BOM

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I used MySQL as my local compent database.

Everything goes right until generating BOM.

A Error occurs as :

ERROR(ORCIS-6156): Unknown database field type

I am not sure what's wrong with OrCAD Capture CIS 16.6 has anyone met the same problem? 

Maybe something worng with my Data type set in Mysql database,but I am not sure. 

PCB~Watch Man Utd v Norwich Live HD STream Saturday 02-Mar-2013

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 It is most common thing that whenever match begins in the sports ground,both team shows high spirits and also try their best to show the professional skills to win the match. It’s not unusual it’s part of game and that makes this game interesting in all means.Let’s see who will win this match.. Watch Stoke V West Ham

 

 

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Just~Watch Swansea v Newcastle Live HD STREAM Saturday 02-Mar-2013

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Enjoy)+Watch Wigan v Liverpool Live Football Match Saturday 02-Mar-2013

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Standard files for manufacturing PCB editor

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 hi guy's

just wondering as a general guideline what are the essential files that are needed for the manufacturer and i suppose the flow in which the must be generated? once the board is ready for manufacture! Thanks.

Regards

Fran 

REG:SAME NET VIA PARTIAL CONNECT

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Good Day to All 
How to avoid below circumstance  while doing copper pouring ? .Via’s  not connecting fully /Not fully voiding ?
One option is to enable same net DRC & manually void in the error area ,its tedious when similar via counts are more .
Is there any property I can attach to the shape , via ,net , So that like this connections are avoided .
 
Please suggest
Thanks
Regards,
Girish Kumar

Driving an Allegro Board design with Capture Net attributes for delay tuning etc

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Hi, in 16.5 is there a way to apply net attributes to a capture net and then have Allegro use that information.

What I am trying to do is in capture give certain nets a max and min length so that when the netlest is generated the info will be passed to Allegro.

Actually I would like to be able to specify a few more things like the width of the net, Min spacing between 2 nets etc ... stuff like that so the engineers can enter the info at the sechmatic level.

I looked at the net properties spreadsheet in capture and filtered it by cadence allegro but I dont see any attributes that pertain to setting min, max length of the net etc.

Not too sure if it is possible to do this or not ?, It looks like there is a way to add additional attribute fields in Capture so perhaps this might be a method to get the attributes in ?, wonder what attributes to use ?

Thanks Scott.

Simple Import from DXF to PCB 16.6 - Incorrect Results

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I finally got the courage to load 16.6 SP3 and start a new design with it.  Having to duplicate an existing layout with respect to many keypad switch placements, I thought importing some simple mechanical info from a client provided "dwg" might save me some time - - should have know better!  Ranting aside - -

I converted the client's dwg to a dxf (2000-2002 format).  Then with autocad viewer determined which of the 100 un-named layers of content contained the features that might actually be helpful for component placement. Using the Import>>DXF functionality, I selected and mapped the desired two layers of the dxf into board_geometry/assembly_notes and assembly_detail subclasses of a new blank board file.

Theimport onto assembly_notes subclass mostly imported OK except for line and arc line widths being weird. However, the import onto assembly_detail subclass was a disaster.  Essentially 27 separate squares managed to import on top of one-another in a location not even close to their actual location (in the dxf) or relative to the location of the other features from the first layer import.

 I used "incremental addition" and "use default text table" selections for the import process (thinking that one of the dxf layes did have some text on it).  The dxf2a log only reports a few "illegal character substitutions" for each of the layers imported.

Any clues to what I'm doing wrong?

Thanks!

PSPICE Model for TL494

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Hi,

I am designing a circuit with TL494. When I run my model in ORCAD it gives me many of this annoying error: Less than 2 connections at node. The nodes are all connected tothis TL494.

I've been told that this model is just for schematic purposes and I cannot use it for simulation. So, does anyone have any idea what I can do?

 I hope I get some answers on this question since there is not similar answered question on the web as so far I've search.

 Thanks

database has errors (artwork generation)

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Hi guys,

When im generating athe artwork/gerber files with the check database before artwork option checked. i get six similar errors. the error as shown in the log file is

ERROR IN BRANCH name = SA

  ERROR(SPMHUT-17): Schedule contains an illegal disconnected branch.

NET may have lost connections. Check for missing connections. 

 

i dont know how to deal with this really. i looked at the etch connection on the board and it seems to be fine.

i updated DRC and no errors found. all 6 errors are the same just different brance name.  Any ideas? 

also if i run the artwork without "check database before artwork checked" will this be ok? 

Regards

Fran  


ERROR(ORCAP-36055): Illegal character in \ic (logic )\.

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I'm having to migrate an OrCAD schematic that was originally layed out in OrCAD PCB to work with Allegro. I get the error

ERROR(ORCAP-36055): Illegal character in \ic (logic )\.  when I try and netlist but I need help in tracking down the illegal characters. I've searched the footprint names and I've searched a netlist generated for PADS2K so what can I try next.

 TIA, Oliver

Via array functions

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Hi guys, 

basic question really. 

im building a basic 2 layer board. my routing is on the top. when i was defining the copper area's for top and bottom i assinged them to net supply_0. which im saying is GND.

 i want to connect the top copper planes to the bottom copper plane using via patterns for shielding and stiching. when in the via array function i assigned the via net as supply_0. and ran i looked at this on the 3d viewer and it looks as if it is connecting the bottom etch to the top etch.

i just wanted to know is this the correct way of doing it? and will this suffice for copper shielding around traces and stiching.

Thanks

Regards

Fran  

Schematic symbol pin naming

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Why does each pin of a schematic symbol have to have a unique name? I gave a large part with many pins of GND. The netlister gives me an error telling me to rename the pins with a unique name. GND1, GND2, GND3........ Kind of silly.

Is there some magic setting that will allow the netlist to compile even though the pins have the same "name", but different "pin numbers"?

Tom

Forum Content

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Why are there posts with links for streaming video/shows/etc. posted on this forum?

Footprint dimensions for Tantalum cap EIA 2824 (metric 7260)

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Can anyone point me to where I can find a drawing that shows the dimensions for a EIA 2824 (metric 7260)?

I find it very interesting that none of the data sheets for the part we want to use has the pad dimensions.

Thanks,

Tom

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