Hi friends,
I am new to DDR Routing in allegro PCB Editor ,Anybody please help me to understand how to set the constarint and routing,Please share any document which is related too
Thanks in advance
↧
DDR Routing ,Constraint set
↧
PSpice Capture Lite Error No Pspice Template
Hi,
I am working on a school project involving a power switch and I am using PNP and NPN transistors in my pspice model. When I go to simulate the project, I am getting green circles above the two BJTs and the following error message in the System Log:
WARNING [NET0093] No PSpiceTemplate for Q1, ignoring
WARNING [NET0093] No PSpiceTemplate for Q2, ignoring
Both devices are taken from the pspice library, which was what most other forum posts suggested. I tried creating a new project file and building the schematic from scratch to see if that would fix the issue, but it didn't.
Any help on how to get this working would be great.
Thank you,
Ben![]()
I am working on a school project involving a power switch and I am using PNP and NPN transistors in my pspice model. When I go to simulate the project, I am getting green circles above the two BJTs and the following error message in the System Log:
WARNING [NET0093] No PSpiceTemplate for Q1, ignoring
WARNING [NET0093] No PSpiceTemplate for Q2, ignoring
Both devices are taken from the pspice library, which was what most other forum posts suggested. I tried creating a new project file and building the schematic from scratch to see if that would fix the issue, but it didn't.
Any help on how to get this working would be great.
Thank you,
Ben
↧
↧
Still fighting with Pad Designer
First, is there a good help site for Allegro? In the Cadence Help the search is crazy. It tells you much to much(i.e. for the Router), but
almost never the solution.
I have a Padstack with a custom shape for PASTE_MASK (on 0.05 grid) and 2 rectangles (on 0.01 grid).
Now I open an package symbol with 0.01 grid, place a padstack, and wow the limits of the padstack aren't on grid!?
Any idea?
regards,
Steffen
Working with Orcad 16.5
↧
IDX Export
Hello,
I want to export design from PCB Editor to CircuitWorks, it's working but not for copper shapes...
Have you an idea, how to export shapes ? (V16.6)
Thanks for help
↧
Creating Guard Rings
I am working an example learning how to do PCB design using Allegro PCB editor from the OrCAD 16.6 suite, and I'm having a problem where, when I try to put a guard ring around a through-hole pin, it erases the trace when I place the last point of the arc. It won't let me place a complete circle. Is there something I'm doing wrong?
I've placed a via from ground to the top routing layer, a straight trace that goes above my pin, then as I place the arcs around the pin, it will not let me complete the circle. If I click to place the last point of the arc, it erases the whole thing and has me start over again.
↧
↧
Converting Layout (.max) to CADstar PCB getting an error?
Hi,
I want to convert the layout file to CADstar PCB using the export option.I had doubt on the original CADstar file?
Where i have to search it. When i used to convert it means the converted file size is been get 0KB document.
↧
update library parts in schematic using Design Entry CIS
Hi everyone,
I have drawn one schematic,after updation of schematic symbol from library, how to retain the previous connections??
Pls suggest asap.
Thanks.
↧
PDN Analysis Static IR drop sim fails
I'm experimenting with PDN analysis on a trivially simple design (2 DC sources, 4 caps and 1 load resistor).
Static IR drop analysis fails with this log message:
10:46:04: Parse all pin shape short ...
10:46:04: Parsing static model for all power/ground/signal traces...
10:46:05: Generating static model by field solver ...
10:46:13: Fail to solve umf matrix in 64bit with error (-127).
Single Node analysis succeeds with no errors.
Power Integrity analysis fails with this message:
<my installdir>\SPB_16.6\tools\pcb\bin\pdnsim.exe is not a valid Win32 application.
I haven't found any references to error code -127.
Has anyone seen these errors before? I'm having no issues with Capture CIS, or other Allegro license options.
↧
Worst Case Analysis Simulation of a Voltage Regulator
I would like to be able to run a worst case analysis on a circuit that contains a oltage regulator. As an example the LM117 has a fluctiation of +-%8 between its nodes, which varies the nominal voltage difference which is set at 1.25V (as intended) anywhere between 1.15 to 1.35 volts. At moment I put in the voltage regulator in the circuit, edit the pspice model and change the reference voltage to 1.15, run the simulation, repeat the same steps and change the voltage to 1.35, run the simulation again and compare my results.
My question is, how can I enter a "dev" percentage in to a voltage regulator so pspice would simulate it automatically under the montecarlo/worst case tab, similar to the resistors and capacitors?
This is the subcircuit of the part i am talking about. The voltage reference is given on the third line as 1.25 volts between nodes 4 and ADJ. I want to edit that line and write something like
"Vref 4 ADJ 1.25 dev=8%" but can't get it to work.
.SUBCKT LM117 IN ADJ OUT
JADJ IN ADJ ADJ JADJMOD;ADJUSTMENT PIN CURRENT
VREF 4 ADJ 1.25
DBK IN 13 DMODX
CBC 13 15 8e-010
RBC 15 5 1000
QPASS 13 5 OUT QPASSMOD
RB1 7 6 1
RB2 6 5 128.3
DSC 6 11 DMOD
ESC 11 OUT VALUE {5.646-0.1125*V(6,5)*V(13,5)}
DFB 6 12 DMOD
EFB 12 OUT VALUE {7.886-0.3727*V(13,5)+0.005097*V(13,5)*V(13,5)-0.02*V(13,5)*V(6,5)}ÂE
EB 7 OUT 8 OUT 7.691
RP 9 8 100
CPZ 10 OUT 3.979e-006
DPU 10 OUT DMOD;POWER-UP CLAMPLING DIODE
RZ 8 10 0.1
EP 9 OUT 4 OUT 100
RI OUT 4 100MEG
.MODEL QPASSMOD NPN (IS=30F BF=50 VAF=8.891 NF=2.612)
.MODEL JADJMOD NJF (BETA=5e-005 VTO=-1)
.MODEL DMOD D (IS=30F N=2.612)
.model DMODX D (IS=30u N=0.612 RS=1m )
.ENDS
↧
↧
Encounter, Allegro, Incisive or Encounter
Hi everyone
I have been using OrCAD, PSPICE and PCB Layout at University. I have just started a job and the company is also using Cadence software, but not OrCAD. I think I spotted "Allegro viewer" as part of the package, but everyone in the company just calls it "cadence software".
I wanted to take some courses in cadence software but apparently there is Encounter, Allegro, Incisive or Encounter and I have no idea what the difference between these are or which one my work uses, which one I am better off training in etc. Is anyone able to give me a full breakdown of the different products, why they are there, what is more useful for me to learn etc.
Thanks and best wishes
Dawud Beale
↧
Changing reference designators without re-placing components
Hi,
I have a board file and schematic that are linked. There are 5 different schematics and layouts (already manufacturered) each are independant of each other but are on the same board with v-grooves cut between them. I want to create a new schematic and board each of which are individual instead of together on one board. This would not be a problem but I would like to be able to change the reference designators on the schematic without re-placing the components on the board file after I import the netlist.
Is this possible?
Thanks
↧
Two Layer Board with copper fill on top and bottom; Problems with Void touching Shape
Allegro 16.3. I have created a simple two layer board with copper fill on top and bottom. This copper fill is my ground plane. I followed a manual that explained how to create the shape, assign a net name and create voids. Everything seems ok, I have several SMT footprints and through hole parts and several vias installed on the board. When I do the update DRC, it returns with no DRC errors detected. When I go to produce the artwork, I choose RS274x, select all films and create artwork. It returns an error:
ERROR: aborting film - Shape with first seg=(841.447 1910.321) [layer=TOP]
has a void with extents [(1771.492 748.691) (2223.750 978.392)] that touches
another shape with first seg=(25.000 25.000). Manually resolve problem.
I followed several of the posts on this forum to attempt to resolve this issue. I moved the entire ground fill (on the top only) away from all other components. This solved the problem. I can get the artwork with no errors. When I try to pin point the offending part, it seems every part on the board will cause the error above. I selected the "Global Dynamic Shape Parameters" menu and set the minimum aperture for gap to 500 mils, along with teh suppress shapes less than 500 mils. This solves the problem, I can get the artwork with no errors. However, my ground plane has shrunk from a 2 inch x 2 inch plane to about 1/8 inch by 1/8 inch in the lower right corner (this is not acceptable). The bottom ground fill does not have these problems. It also has no SMT parts on the bottom.
I know this must be a rookie mistake. But, I followed most of the fixes that were suggested on this forum and nothing works. I also tried to merge Shapes, but this does nothing. What am I doing wrong?
Thanks, Richard
↧
Creating PCB panels in PCB Editor
Can you duplicate your pcb in editor? I've just finished designing a pcb and I want to create a panel with 18 PCB total (9 rows 2 colums) with a technical edge on each side so than i could send the manufecturer a gerb files. How can i make a panel and put 18 same pcb on it? I have to make 18 schematics in capture and after i can copy pcbs in editor? Can it be done in pcb editor or do I need some patch for it..?
Thanks Szabolcs
↧
↧
Pick and Place include variant changes
Hi,
Is there a way to include data (changes) from the variant editor in a placement or component report ?
Regards
Jürgen
↧
IDX Export
Hello,
I want to export design from PCB Editor to CircuitWorks, it's working but not for copper shapes...
Have you an idea, how to export shapes ? (V16.6)
Thanks for help
↧
Optimizing a model parameter
Hi all,
I'am new to Orcad Capture and Pspice (v16-6).
My problem is that I would like to optimize the parameters of some models (i.e. of the standard diode model or of a standard level 1 mosfet) with the Standard or Curve fit Optimizer.
I tried in different ways with no success. I have no problem in running optimizations (both with Standard or Curve fit Optimizer) where i try to optimize for instance the value of standard resistors or capacitors but when I want to optimize some models parameters I don't know how to proceed.
For instance I would like to optimize the Rs parameter of a diode D in order to fit a measured I/V characteristic but I 'm not able to import this model parameter in the "Parameters" list in the Pspice Advanced Analysis Optimizer.
It is possible to do this kind of optimization in Capture/Pspice ? I read a lot the help but with no answer.
Thank you very much!
Best regards.
Dan
↧
Drill File Not Recognized
I'm having problems getting my board made. We have a small machine on campus capable of printing a board (I think only 1 sided), but the technician is telling me that the drill file generated by Allegro are recognized by the machine. Has anyone else had a problem with Allegro Drill files? If so what can I do to fix this?
The board I need to make is single layered. Attached is an image of the NC Drill window. Is there anything that is wrong here?
↧
↧
Cline width change
Hi all
If there is a board routed with different Cline widths for example 5 mill, 10 mills and 25 mills, then is there any way (any option, any skill program ,any script) by which i can change line width of 5 mills to 8 mills without searching the 5 mills tracewidth.
Regards
Nayyier
↧
Stimulus simulation error
hi guys i have been doing a exercise out of a book that involved The vstim stimulus part from the sourcestm library. when i edit the the properties of the stimulus like it is supposed to the stimulus give out 100hz sin wave but when i close stimulus editor when i it have set up. then when i want to go back and edit the properties i get you can only have one stimulus editor open at a time but its not even open anybody got any ideas its orcad 16.6
↧
ODB++ Inside
Hello - Yesterday I attended a Mentor Graphics presentation on ODB++. Naturally, the presentation was MG slanted but during the presentation they mentioned "ODB++ Inside" for Cadence products. I'm interested in any comments on this tool/feature in particular and the Cadence migration toward ODB++ output in general. Thanks in advance.![]()
↧