Hi,
I've been using allegro design entry cis on a project and so far it was working fine.
Today, when I opened the project, I realized there was no schematic on it, only the design cache and the Outputs (since I already created the netlist for PCB Planner).
On the session log, there is the following error:
INFO(ORDBDLL-1187): Read failed for schematic: BuckBoost
Is there still a way to recover the schematic or is it lost?
Thank you
Hello is any one knowingsolution for this please help me.
When i click on route->PCb router->Route Automatic then its showing error as cant start specctra with design
Thanks
abubakar
hello averyone,
i am cadence user, i use windows 7 platform on my computer, running cadence 16.3 on my office. i really wonder why its so so slow when i use smooth dynamic fill where my computer friend can run it really smooth in windows XP (his computer spec is lower than mine). what should i do? thanks fo your help
my computer spec :
OS : windows 7 enterprise 32 bit
proc : intel quad core Q8400
RAM : DDR2 4 GB
HDD : 320 GB
VGA : Nvidia quadro FX1800
Hi! All,
Is there a way to print the DRC markers? The Orcad Capture displays all the DRC markers in green circles, but I don't seem to be able to print them out.
Thanks!
Hi! All,
Does anyone have used PDF Export in Orcad Capture? I kept getting the following message, "The postscript to PDF converter tool acrodist.exe not found in the path. Either supply the fully qualified path in the command or make sure the path has been added in the PATH environment variable"
I verified that Adobe Distiller is operational in my computer and the path should be correct. Has anyone experienced the similar issue? Adobe Acrobat print out doesn't include the hierarchical capability, so I would like to try PDF Export in Orcad itself.
Thanks!
I have sorted through and figured out how to rename the ref des on a board. How do I import this info into Capture now? It only creates a .log file, not a .swp file which Capture is looking for. Renaming the .log file to .swp causes an error on import into Capture.
Using latest 16.6 version.
Tom
Does anybody else ever run into login problems? I can be shut out for a day or weeks at a time. I have been in contact with tech support, but not much help there.
Yesterday I was able to log on and post a question as well as answer a few. This morning I went to log in and either got sent to the Cadence home page or an alert page telling me that I need an account to log in. I even went so far as registering for a new account this morning and still couldn't log in with that on either.
Tonight I try and I can log in with no issue, but all day I was unable to.
Has anyone else experienced this, or is it just the forum gods getting tired of my inane questions and giving me a time out?
Tom
Hi!
I would like to ask what are the possible cause for this error when packaging?
ERROR(SPCODD-563): Following blocks have netlisting errors. I can't locate the errors using markers. This was designed in other location and when was sent (through archive in project manager) to me for troubleshooting, I noticed that there are some menu and commands not available in my window.
What must be the possible reasons for these?
Thanks,
Mabel
Need help to create schematic (.pdf) from existing cadence 16.5 drawing.
Thanks!!
Hi everyone,
does cadence support Fedora 19
Hi,
I want to convert the layout file to CADstar PCB using the export option.I had doubt on the original CADstar file?
Where i have to search it. When i used to convert it means the converted file size is been get 0KB document.
Hi All !
I layout PCB for my project and I have important problem , I don't fix it
I have via in SMD pad and Allegro PCB DRC error : SMD pin to thru via spacing overlap
I don't know . Please help me !
thanks !
I am using Allegro PCB Editor 16.3. Although I have used this product for a while I've never needed to add Maximum Package Height as something to flag using DRC. I've looked in the documentation and the only constraint-setting information I can find is for spacing/width/pairing type stuff. Where can I find the documentation to set up maximum height constraints? I know I can manually check each package on the board for it's Max Height property that is far from ideal.
I will be grateful for any insight that can be given.
Budd S.
Hi everyone,I've just started using Allegro pcb editor and i want to use the libraries i had in layout,how can i convert them to be compatible with allegro?
hello averyone,
i am cadence user, i use windows 7 platform on my computer, running cadence 16.3 on my office. i really wonder why its so so slow when i use smooth dynamic fill where my computer friend can run it really smooth in windows XP (his computer spec is lower than mine). what should i do? thanks fo your help
my computer spec :
OS : windows 7 enterprise 32 bit
proc : intel quad core Q8400
RAM : DDR2 4 GB
HDD : 320 GB
VGA : Nvidia quadro FX1800
Hello,
I am looking to create a Title Block for my designs. I am looking thru the pcb editor defining and developing libraries. What I'm reading I could take it 2 ways.
Do I have to draw the Title block myself and save it? It tells me to make 4 different sizes A,B,C,D.
I gives me samples of what it supposed to look like.
or, Are they already made up I just have to find where they are located at and load them in?
Any help is appreaciated
Thanks, Dennis
I have both an XP box and a windows 7 Box attached to our corporate network. Both have the same releases of the Cadence tools and same Cadence service pack/Hot fix releases (up to date as of 7/29/2013)
Issue:
Windows 7 box - exporting libraries to the network server takes over 15minutes (hard disk about 10 seconds)
Windows XP box - exporting libraries to the network server takes under 1 minute (hard disk about 10 seconds)
Things we have tried:
The PC boxes next to each other, same version of the tools (tried 16.3, 16.5 , 16.6 all releases behave the same).
Swapped Nic cards, no difference
Swapped Ethernet ports, no difference
Changed many of the settings in the windows environment, i.e. Auto detect speed changed to 1G, 100M, 10 M, Full / half duplex,etc...
My IT team is very puzzled and has run out of ideas.
Other symptoms: Win 7 Box - generating artwork first time is fast, but if there are existing files, very slow upwards of 5 minutes. Saving a file to a new file name - fast (realm of seconds), re-saving to current file name slow (realm of minutes).
Suggestions encouraged and welcomed. Thanks!
-------------------------------------------------------------------------------------------------------
Box details:
Box1 Intel Xeon CPU E3-1225 @ 3.2 GHz with 16 GB RAM, Service Pack 1 (Win 7)
Box2 Windows XP box is a DEL 780, Intel® Core™2 Quad, 4GB Service Pack 3 (Win XP)
Hello all
I am using PCB Editor 16.3. I have some areas of copper voids on my ground and power layers (negative artwork). The shapes are visible in the .brd file and is of the class "Anti etch/Ground" and "Anti etch/Power". I have added these classes to my artwork control form but I don't see the shapes in the resultant gerber files. Anyone have any ideas of what I am doing wrong?
thanks
T
Are there any detail drawing or assembly drawing formats available? What I mean by formats is the border with title block and notes.