Does anyone know how to add mechanical parts to a schematic symbol so that they appear in the bom?
I am thinking of connectors with associated screws etc. At the moment we create a bom and then manually add the mechanical parts.
I am using v 16.5 but not the CIS part manager. Therefore I only use the Tools > Bill of Materials menu pick.
Thanks.
Open the Gerber, how to check the via is from which layer to which layer? Thanks,
Especially some beried /blind visa.
Newbie here,
I'd like to have a thin board (~0.6 mm) with 2 FR4 layers and gold on top. I'd like to have a large rectangular region where the only top FR4 layer is removed. In the middle of that region, I'd like a smaller rectangle that is a hole through the board. Basically, in the region with the arrow in the attached picture, I'd like the following layering (M=metal, F=FR4, space = nothing).
Top - MMMM MMMM
Mid - FFFFFF FFFFFF
Bot - FFFFFFFFFFFFF FFFFFFFFFFFFFF
How can I accomplish this? My first thought was a Cavity in the Mid layer and a board outline for the small hole. The 3D viewer doesn't look exactly like I want. What can I change?
Good afternoon,
Under the Design Parameter Editor / Edit global dynamic shape parameters / Thermal reilef connects, I select the button for 'Use thermal width oversize of:' and set it to "0" so that my thermial reliefs will use the width I enter in the constraint manager. However, after I select the OK buttons and reopen the window the 'Use fixed thermal width of:' button is selected. I am guessing there is a setting I must have set, but can not find it.
Thank you for any help,
Has anyone else seen this error? We installed Orcad V16.3, including the hotfix, yesterday, and it was working just fine. I came in today and tried to launchOrcad Capture CIS, I get the following error window:
This application has failed to start because cdn_sfl401as.dll was not found. Re-Installing the application may fix this problem. I don't want to re-install every day!! Any ideas out there?
Thanks,
Todd Moore
Is there a way to write a text inside a shape in a inverted way i.e. like doing voids corresponding to the text letters inside the shape ?
I have a design which has 7 layers. The top layer has only short stubs.
There are two layers for traces but they are sensitive signals and there is a solid ground plane above and below these two layers. I have connected these two planes at one point near the incoming supply. I also have a single ground plane as layer 7 which is noisy.
How do I connect a number of ground signals from Layer 1 to Layer 7 WITHOUT connecting to the other two ground planes, which would inject noise onto these planes?
When I try using the normal vias, they connect all planes from 1 to 7 and also 2 and 5, I just need layers 1 and 7 connected but they need to connect at the supply (one via connecting layers 1, 2, 5 and 7).
Hello,
Anyone out there are using the Component_changes.il, I tried to use it and it didn't work. I looked inside the file and its was written by Peter to work with Allegro 11 and later got modied to work with 14.2 by Ron Guthrie. Cadence Design Systems.
I am using ver 16.6
It would be nice to compare 2 xxx.brd files to see what have changed since the previous versions.
Thanks
Regards,
Tibo
All,
I am looking to be able to save a complete design as a sub drawing and reimport it into either the same drawing or merge two or more seperate drawings to make a mixed panel. On these designs I will have components that have some of the same reference designators and nets. So far I have been unsuccessful in doing this and having reference desinators and nets export/import properly. The reference designators will be #REFDS* regardless of what options I choose when saving and importing the subdrawing.
As a note I am turning on all of the layers (Class & Subclass) before making the selection for the subdrawing and all of the designs will have the same Class & Subclasses present. I am also using the latest Allegro PCB Designer 16.6.
Thanks for the assistance a head of time.
~Rick
Hello all,
I'm working with allegro 16.6 and am exporting a an already routed PCB design as IDF to solidworks folks.
It turns out one of the symbols in the pcb design was missing height information. I opened the symbol in allegro and added the height info.
Then I went into the pcb design place->update symbol and selected the proper symbol. The symbol updates , I exported the IDF, and now the solidworks folks are happy.
One problem however: the symbol's pins in allegro all have ratsnest on them now. I can go and reroute the clines next to the pins and this seems to fix the issue, however, it would take a long time to do all of the pins and could potentially be error prone.
I'd like to point out that before the symbol update there were no ratsnest / unconnected pins on in the design and specifically on this particular symbol.
Is there anyway to connect the pins / fix the ratsnests?
Thanks in advance.
Dear All,
In my layout there is spacing violation for Dynamic shapes and Static shapes.
Some Dynamic shapes are too close to Static shape ( the minimum is needed to be 8 mil).
But my DRC is NOT catching them.
Could anybody please tell how to set the constraint so that the DRC can catch the spacing violation between Dyanmic Shape and Static Shape.
Kind Regards,
I have a design that I have mapped all my step files and viewed the board in the 3D viewer. Everything looks good. When I click File>Export Image, Allegro exports a blank JPG file. It creates a file that is 32KB and contains just a blank page. I also tried a tif file. Same result.
Has anyone suceesfully exported a JPG from the 3d Viewer? Any ideas on what might be the problem?
Hi,
I have a problem with a small design I'm working on. Under Display->Status I have 1 unrouted net with two unrouted connections, but when I check the unconnected pins report it shows 0 (see attachment).
- I have manually tried to find what I could have missed but have not found anything unrouted.
- I have dbdoctored the desig, still the same.
Could this be a bug or do I have some floaring trace or whatever lying around.
Best regards,
LMC
Anybody have a SKILL script that will make a small circle with crosshairs, at the symbol origin on PACKAGE GEOMETRY/BODY_CENTER, that will run from inside the symbol editor?
Dear All,
I want to ZOOM IN to a partiicular co-ordinate in Allegro using command.
Could anybody please tell what is the command and how it can be achieved
Kind Regards,
I created my connector footprint by using the "CONN RCPT 46X2" model from the library then I renamed it as 123456.dra and put it in my project folder. When I created the Netlist and the error was listed in the netrev file as Porblems with the name of device 'CONN RCPT 46X2_123456_CONN RCPT 46X2': Name is too long.'
I tried to look under its property and the 123456 was listed under footprint column correct. I didn't know where else I can change its name or to look for! Can someone please help?
Thanks so much!
Hi,
how to add a company logo, a picture, or a marking seregraphy in PCB board with "Allegro PCB Design",
see exemple in attached image:
Best regards,
Haithem.
Hello All,
When trying to export the ODB++ with C:\Valor\ODB++Inside, I get the error:
Windows platform
*********** ERROR 18Nov2013.164607.861 6244 8.1(55) Windows Vista
Cadence Interface - File layers_326288ck1_01a.out has wrong header
Status raised : module - G:\s81\eif\eif_cadence.c, line - 3155
Status raised : module - G:\s81\eif\eif_cadence.c, line - 2889
Status raised : module - G:\s81\eif\eif_cadence.c, line - 2608
*********** ERROR INTERNAL 18Nov2013.164607.861 6244 8.1(55) Windows Vista
(ind_list != NULL && ind_list->magic == IND_LIST_MAGIC) at G:\s81\gen\gen_sort.c 1236
Status raised : module - G:\s81\eif\eif_cadence.c, line - 2169
Status raised : module - G:\s81\eif\eif_main.c, line - 490
Status raised : module - G:\s81\translators\brd2odb\brd2odb.c, line - 462
Failed to translate job !!!
Status raised : module - G:\s81\translators\brd2odb\brd2odb.c, line - 1820
*********** WARNING 18Nov2013.164607.862 6244 8.1(55) Windows Vista
T r a n s l a t i o n e n d e d W i t h E r r o r s
I'm working on a design in OrCAD Capture 16.5. When making a netlist, I got errors because one of the part instances used an invalid footprint name (had a space in it).
I went into the part library and fixed the footprint naming. All I need to do now is update the instance in my design to reflect the updated source part in my library.
I found the part in my Design Cache and have tried "Update Cache" on the part (which succeeded without errors). The footprint field didn't get updated, however, on my part instance. I even tried "Replace Cache" without any success in updating my part instance...
Am I missing something here? How can I apply the updated cache to actual instances of parts in my design??
I can place a new part (from the source library or from the design cache) and it shows the correct footprint. I just can't get it to apply to existing part instances.
