Is there a way to add specfic properties to a part symbol, such as "created:", "modified by:", "comment" or other company specific requirements?![]()
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Adding custom Properties to Part Symbols
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Analysis Of German PCB Market Data September
September sales of PCB in Germany were up by 10% year-on-year, according to the Central Association of PCB and Electronic Systems. Sales for the first three quarters of the year, meanwhile, PCB are around the same level as that of the same period in 2012.
Orders increased by 27.6%, the highest ever PCB increase in the year, as key sectors PCB usually complete their orders as well as concluded framework PCB agreements in September in preparation for the holiday season.
Book-to-bill ratio in September jumped to a value of 1.15 PCB.
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China's largest PCB
China's largest PCB,The best price and quality.Are you interested in to have a look.Still can give you a discount.
http://pcb.hqew.net/
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How to delete a PIN in package design editor ( Allegro 16.2)
Dear All,
While designing a footprint in package design editor of Allegro 16.2, I wrongly placed a PIN (PAD).
But I want to delete it now.
How it ccan be done.
Kind Regards,
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Importing Complete Designs as Subdrawings
All,
I am looking to be able to save a complete design as a sub drawing and reimport it into either the same drawing or merge two or more seperate drawings to make a mixed panel. On these designs I will have components that have some of the same reference designators and nets. So far I have been unsuccessful in doing this and having reference desinators and nets export/import properly. The reference designators will be #REFDS* regardless of what options I choose when saving and importing the subdrawing.
As a note I am turning on all of the layers (Class & Subclass) before making the selection for the subdrawing and all of the designs will have the same Class & Subclasses present. I am also using the latest Allegro PCB Designer 16.6.
Thanks for the assistance a head of time.
~Rick
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Netlist failure - duplicate Name issue
I have a multi-page design originally created in Capture 10. Now that I'm making a netlist in Capture 16.5, I got an mismatch error between xprt and xnet. After a quick search, it's quite clear that the problem is a shared Name field by two instances on different pages.
According to http://www.freelists.org/post/icu-pcb-forum/netlist-error,2 this was an additional check implemented in Capture 15.x and there is a Cadence Sourcelink solution - 11116526. Unfortunately, I can't find a link to this solution. Can anyone explain how to fix this?
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strange unconnected pins
I have a very simple desige, only have few compnents. I noticed that in the unconnected pins report have many pins that connected.
the design used to be 16.2 or even early version. I upgrded to 16.6 recently.
if I delet the trace, I couldn't reconnect to the unconnected pins. but if I check the net, it shows the pins are in the same net.
for example
ZTP7.1 to L2.2 marked in the attached picture. How can I make the connection between this pin?
thanks,
David
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Team Design - Unable to recognize permissions of shared area
I decided to try the Team Design approach. I requested that a Samba share workspace be set up as there are a mix of PC and Unix users on the team. I am able to access this share from my PC (Windows 7) without any problems, ie I have read and write permission. In Project Manager I open the project then select "Tools-Team Design". Within the Allegro Team Design Authoring app I then select "TeamDesign- Enable Team Design". The first setup item is to specify the Shared Area. I browse to the aforementioned Samba share, click Next> and I get the following error: "ERROR(SPDWSD-14): Unable to write to 'T:/'. Ensure the required permissions are available and repeat the task."
T:/ is the drive letter that I have the Samba Share mapped on my PC. I have tried the full address of the share and get the same error. I'm at a loss on how to proceed to solve this issue besides giving up on the Team Design approach. Any help or thoughts?
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Capture CIS_Show Footprint
Can someone explain how I can set the correct paths for my symbol library so that I can view footprints inside capture. I have set the psmpath to the folder where my .psm and .dra files are located in the environment editor. However, when I select my part and choose show footprint I get an error stating allegro footprint not found in search path or something to that nature. However, if I use a symbol from the discrete capture library like a resistor and then select a footprint located in the cadence/..../share/pcb/pcb_lib/symbols folder it works. Are my libraries not set correctly even though I can place parts manually in pcb editor or is their something else I am missing.
Thank you![]()
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Find a net on schematic page?
When I do a DRC on a schematic page I get a warning: "Net has fewer than two connections N14105". No warning marker is shown on the schematic and I can't find this net on the page. How do I find this net?
thanks
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How to Lock constraints
Hi ,
I wanted to know if its possible to lock constraints in constraint Manager so that once constraints are set it will not be changed knowingly or unknowingly.
Thank you
Regards
Prasanth
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Exporting .brd file to DXF
Does anyone know how to export a .brd file to DXF?
Every time I try, I get a message saying "Given layer filename does not exist. You must create one".
I have no idea what this means and the help menu is not much help.
Thanks,
Doug
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Why the same net via and shape can not connect togeter?
I have met a problem when use 16.5 in divide power layer, the same net with the dynamic shape and via cannot connect together.
just like pic as follow or link. The via avoid the shape. And I want to know how to solve it, thanks a lot!
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Design Entry HDL-How to print a pdf for selected component
Good morning,
I´m looking for a method in Allegro Design Entry HDL 16.5 to print a pdf file only for the selected components and net in a schematic.
Is that possible?
Thanks
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How do you change the size of existing text?
I've figured out how to change the "Text Block #" (size) of new text I type by going through Setup > Design Parameter > Text tab > Parameter Block, but how do you change the size of text that already exists? Or do you have to delete it and rewrite everything?![]()
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[Question] In specctra router, the screen can't be zoom in or out by dragging the pushed middle-button of the mouser. Why?
It looks the specctra doesn't run, but the edit--> zoom in can works. Why?
Have any guy encounterred this problem?
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allegro 16.6 does not create bus functionality?
I use cadence16.6, did not find a function in allegro bus created inside the Constraint Manager, this version does not have this functionality? Please help me!![]()
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Create two separate symbols for one Part in Part Developer
Hi,
I am trying to create a part symbol for schematic (in Design Entry HDL) and this part comes with alot of pins,
is it possible to generate two symbols (two rectangles) for one part from Part Developer?
Such that the two symbols appear together in the Design Entry when the component is added?
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How can I preserve designators from changes?
Hi
In the Orcad capture schematic environment when we try to copy a page in a project file and paste it into an another project all designators automatically changes.
How can I preserve them from changes?
It is important to me to save all designators without changes.
Thanks a lot
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Half bridge: Totally different results with ideal switch vs MOSFETs
Hello all,
I'm new to PSPICE and I'm trying to simulate a simple half-bridge inverter. When I simulate the topology with ideal switches, the output voltage corresponds to a train of rectangular pulses with a height of Vdc (like it should). But when I simulatethe same topology using MOSFETs (two IRF150 MOSFETs) the output is a train of rectangular pulses of roughly 12% of Vdc. Can it be that the MOSFETs have such a high voltage drop in PSPICE, or am I modelling the circuit wrong??
Here is the netlist from the ideal circuit:
D_D3 $N_0001 $N_0002 D1N4002
S_S2 $N_0001 0 0 0 Sbreak
RS_S2 0 0 1G
D_D4 0 $N_0001 D1N4002
V_V4 $N_0002 0 100
V_V3 $N_0003 0
+PULSE 0 15 0.55ms 0.01ms 0.01ms 0.45ms 0.9ms
V_V1 $N_0004 0
+PULSE 0 15 0.1ms 0.01ms 0.01ms 0.45ms 0.9ms
S_S1 $N_0002 $N_0001 $N_0005 0 Sbreak
RS_S1 $N_0005 0 1G
R_R_Load 0 $N_0001 1k
R_RG1 $N_0004 $N_0005 10
R_RG2 $N_0003 0 10
and here the one with the MOSFETs
D_D3 $N_0001 $N_0002 D1N4002
D_D4 0 $N_0001 D1N4002
V_V4 $N_0002 0 100
V_V3 $N_0003 0
+PULSE 0 15 0.55ms 0.01ms 0.01ms 0.45ms 0.9ms
V_V1 $N_0004 0
+PULSE 0 15 0.1ms 0.01ms 0.01ms 0.45ms 0.9ms
R_R_Load 0 $N_0001 1k
R_RG1 $N_0004 $N_0005 10
M_M3 $N_0002 $N_0005 $N_0001 $N_0001 IRF150
R_RG2 $N_0003 $N_0006 10
M_M4 $N_0001 $N_0006 0 0 IRF150
The only difference between the two are the MOSFETS M_M3 and M_M4 instead of the switches S_S1 and S_S2. This thing is driving me totally nuts, any help would be greatly appreciated.
Cheers!
Javier
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