Hello! I want to install cadence 16.5 software to a different pc and since i have purchased only one license, i have to transfer the license server to the new machine.How can i do it?
From what i understand, each license server has its own license file based on the host id, can i change something in the license file manually or should i contact cadence to request the change?
Thank you in advance.
↧
Change host id in license file for cadence 16.5
↧
Question #2: How do I move the pins of a symbol?
At least, I think it's a symbol. It's a rectangle with two pins inside it that I need to move closer together. How can I do this? So far all I can do is move the whole symbol, or delete it. Is the symbol in a .DRA file and if so, how do I edit it?
I didn't create this PCB. I inherited the project from someone who left the company. Long story.
↧
↧
Export schematic to EPS file
Helloto all,
I madetheschematicin Captureand I would like toexport itas an image inEPS format.
I useOrcadCapture16.5.
Howcan I do?
Thank you!
↧
Need help : Custom menu - System Connectivity Manager
Hi all,
Aplologies first if this is not the right place for the query.
I am planning to call an internal tool from the SCM menu and i am able to call the tool by customizing the "tddCustomizeTBNEW.txt" file under $HOME/cdssetup/tdd.
i want to pass some arguments to the tool,now the SCM tool allows this by using the "Add Tools" command but i would like this step to be automated so that users just have to click on the menu command and the tool gets the necessary path from a fixed location in the project directory. Is there a way to define such files as variables in one of the sections in the the "tddCustomizeTBNEW.txt" file.
Thanks in advance.
Kenan
↧
save schematic as a model in library for reuse in orcad capture
I want to save my schematic drawn as a part in a library so that I can reuse it in my complex circuits.
Please help me out.
↧
↧
Adding custom Properties to Part Symbols
Is there a way to add specfic properties to a part symbol, such as "created:", "modified by:", "comment" or other company specific requirements?![]()
↧
How to Lock constraints
Hi ,
I wanted to know if its possible to lock constraints in constraint Manager so that once constraints are set it will not be changed knowingly or unknowingly.
Thank you
Regards
Prasanth
↧
Converting Existing Vias to BB Vias
Hello all,
I am revising a .brd file on Allegro 16.5 that has already been routed throughout 6 layers. All the vias used where Convensional vias with no BB vias. I am trying to convert most of these vias to BB but there seems to be no easy way to do it. I have already defined my via structure and stack up. I read somewhere that the gloss application may be able to do so; however, it almost seems like that option is not available to me. When i go to Route > Gloss > All i get is the following options > Add fillet/ Delete fillet / Add tappered trace/ delete tappered trace line parameters/ fillet parameters. Any clues?
↧
is it possible to open the constraint in excel ??
Hi everyone,
is it possible to open the constraint (like same apperance shown in contraint manager) in Ms-Excel.i want same apperance in my excel also as shown in image file .i am splitting address and data like that it should come in excel sheet.
please suggest any one for this queries
↧
↧
how to remove the pundle nets ??
hi everyone,
in contraint manager i set the address 0-14 nets in group .it is create like puldle of nets as shown in below image.how to remove the pundle nets ??
wrongly i place the via over the fanout but i could not delete the via.in command window U8 is locked property. i did not lock any think in footprint library. i checked the all the footprint properties.it is like that only.
↧
How to create Touchpad buttons in Allegro 16.6
Hi, Could anyone tell me how to design Touch pad buttons in cadence allegro 16.6.?
I have designed many simple circuits, but i dont know how to design a touch pad. Some Touch pad specific datasheets explain the basic procedure, but i couldn't understand them precisely.
↧
How do I supress my keep out areas in the 3D View? (Version 16.5)
I am trying to export my design to an IDF file format, but I can't suppress the keepout areas in the 3D view. When I try to set the "Default symbol height" in the Design Parameter Editor to 0, it ignores my inputs and always resets the value. I have set the "Package Height Min" to 0. I have also tried setting the "Package Height Max" to 0, but it always uses the current value of the "Default symbol height".
↧
create footprints in pcb editor.
how can i create a footprint in pcb editor? i remember in orcad i used the library manager. But i have seen in another post that pcb editor haven't got anything like library manager. is that true? ¿how do you create a footprint in pcb editor?
regards.
↧
↧
Ground plane help
Hello,
I am new to Allegro and I am struggling with creating a ground plane. For example, in the attached image, jumper J18 pin1 (a plated hole) is assigned to the GND net so I was expecting the ground plane to cover it continuously. However, as you can see it only routes a couple of lines across the hole. Is there a way to make the dynamic copper cover it continuously?
Many thanks for your help,
Matt
↧
PAD & footprint help me I am confused
Hi, this is my firs post there,
I used altium 3 year but now I need to design high frequency and impedance matching and DDR3 and etc so I changed my plane and I want to use allegro Cadence, but I have many problem and I don't have good tutorial that start from orcad CIS shematic and end it in allegro PCB (A-Z).
in altium designer we don't have PAD! I am confused!! I understood if I want to create new footprint I should attach it to pad that I created before.
But I found many footprint in the internet, with themselves PAD. Is it need to attach my new PAD to them? how I can do? if it doesn't need why I should create PAD?
Excuse me for my little knowledge in Cadence alllegro and also my bad English.
any help would be greatly appreciated.
Sincerely yours,
Siyavash.
![]()
I used altium 3 year but now I need to design high frequency and impedance matching and DDR3 and etc so I changed my plane and I want to use allegro Cadence, but I have many problem and I don't have good tutorial that start from orcad CIS shematic and end it in allegro PCB (A-Z).
in altium designer we don't have PAD! I am confused!! I understood if I want to create new footprint I should attach it to pad that I created before.
But I found many footprint in the internet, with themselves PAD. Is it need to attach my new PAD to them? how I can do? if it doesn't need why I should create PAD?
Excuse me for my little knowledge in Cadence alllegro and also my bad English.
any help would be greatly appreciated.
Sincerely yours,
Siyavash.
↧
SigNoise Errors/Warnings
Hi,
All of the sudden whenever I open Cross-section and try to change Coupling Type or go do do a diff route on this particular board, an error dialog box named "SigNoise Errors/Warnings" pops up which shows this list:
WARNINGS:
Iml model STL_2S_1R_TRACE6 is duplicated 2 times in libraries
interconn.iml ..\..\..\..\Cadence\SPB_16.6\share\pcb\signal\cds_interconn.iml.
Iml model STL_2S_1R_TRACE48 is duplicated 2 times in libraries
interconn.iml ..\..\..\..\Cadence\SPB_16.6\share\pcb\signal\cds_interconn.iml.
Iml model STL_2S_1R_TRACE36 is duplicated 2 times in libraries
interconn.iml ..\..\..\..\Cadence\SPB_16.6\share\pcb\signal\cds_interconn.iml.
Iml model STL_2S_1R_TRACE24 is duplicated 2 times in libraries
interconn.iml ..\..\..\..\Cadence\SPB_16.6\share\pcb\signal\cds_interconn.iml.
Iml model STL_2S_1R_TRACE16 is duplicated 2 times in libraries
interconn.iml ..\..\..\..\Cadence\SPB_16.6\share\pcb\signal\cds_interconn.iml.
Iml model STL_2S_1R_CPW76 is duplicated 2 times in libraries
interconn.iml ..\..\..\..\Cadence\SPB_16.6\share\pcb\signal\cds
......
......
It continues for a lot more lines showing different models. These errors are also replicated in the dialog area at the bottom of the screen.
It's only happening for this board and no others.
Anyone know how I can correct this? Thanks!
Robert
↧
NET SHORT DRC CHECK IN ALLEGRO16.6
Hi Good day !
I am using allegro 16.6 version
If I run Design Rule Net short check report , there is no short in the design , but when I check manually all DRC I found net short DRC having spacing of 0.25mils(refer image)
I wonder Y the report shown there is no net short ? what is the minimum value its taking for net short DRC generation 0 mil ?
Best Regards.
Girish Kumar
↧
↧
Cross section not working properly
Hi All,
I am not able to add dielectric below bottom layer. But I can able to add above top layer.Can anyone help me please?
↧
Cadence_tool_Issue
In one of my recent project.i faced some issue with cadence tool. I created a test design to explain the issue in detail.
Actual issue is that the net “VCC_LOAD+” is connected to Global power net “VCC”.
Please see the below screenshot of the schematic.
The Resistor R193 is the sense resistor and the Voltage “VCC_LOAD+” & “VCC_LOAD-” are the sense voltage across the sense resistor R193.
I intentionally provided the “VCC_LOAD+” Net with off page connector to represent the VCC_LOAD+ as the sense voltage.
During DRC check, it raised a question as “Possible short between VCC and VCC_LOAD+”.So we thought that as both the nets are getting shorted.
But during Netlist creation, Cadence tool isolated these two nets and these two nets not at all shorted at even one place.
During netlist creation, there is also no warnings in session log such that the cadence tool is isolating these two nets.
As it is isolating during netlist creation only ,we can’t able track in schematics. It’s very toughest one to find this type of issue in 100 or more page schematics.
If we shouldn’t connect net alias to the global power net, Cadence tool shouldn’t create a net list and it should show error atleast during netlist.
Currently in 16.6.018 version too, this issue arises. Kindly tell us the solution to solve this issue or please clear the bug in cadence tool.![]()
Actual issue is that the net “VCC_LOAD+” is connected to Global power net “VCC”.
Please see the below screenshot of the schematic.
The Resistor R193 is the sense resistor and the Voltage “VCC_LOAD+” & “VCC_LOAD-” are the sense voltage across the sense resistor R193.
I intentionally provided the “VCC_LOAD+” Net with off page connector to represent the VCC_LOAD+ as the sense voltage.
During DRC check, it raised a question as “Possible short between VCC and VCC_LOAD+”.So we thought that as both the nets are getting shorted.
But during Netlist creation, Cadence tool isolated these two nets and these two nets not at all shorted at even one place.
During netlist creation, there is also no warnings in session log such that the cadence tool is isolating these two nets.
As it is isolating during netlist creation only ,we can’t able track in schematics. It’s very toughest one to find this type of issue in 100 or more page schematics.
If we shouldn’t connect net alias to the global power net, Cadence tool shouldn’t create a net list and it should show error atleast during netlist.
Currently in 16.6.018 version too, this issue arises. Kindly tell us the solution to solve this issue or please clear the bug in cadence tool.
↧
Layout to ODB++ Export
Hello,
I’m trying to export PCB build data from Orcad Layout 16.2 but the exported ODB++ files are not complete according to the board house.The help file in Orcad Layout points to a link do download the translator but it seems to be broken. Is there any other way to download the translator?
I’ve tried the steps provided in the below forum, seems that other people have had the same problem.
http://www.edaboard.com/thread70848.html
I will appreciate any help with this.
↧