In my current design, I need to break static shape from center. While using shape void command, I am geeting error " Can't break shape into fragments." Is there any other way around to do the same ?
Thanks in advance
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Breaking Static shape into fragments
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[Question] In specctra router, the screen can't be zoom in or out by dragging the pushed middle-button of the mouser. Why?
It looks the specctra doesn't run, but the edit--> zoom in can works. Why?
Have any guy encounterred this problem?
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Error Creating a Printed Circuit Board Using OrCad Capture and PCB Editor
Hello,
Its been a long time since I've worked designing PCB's. I'm using Orcad Capture for elaborating the schematics and then, and this part is where I'm having a problem, trying to creat the PCB Boadr, creating the NetList, etc etc. I follow all the steps and I even tried doing it with a simple RC circuit to see if my design was the problem. But gives me the same error.
Now, what is the error yu might ask. Well, after creating "successfully" the Netlist, the PCB editor opens BUT, and this is the imporant part, THERE IS NO PCB in sight.
I really dont know what migh it be. If any one can help me with this I would really apreciate it.
P.S: using ORCAD 16.6 on Windows 7 x64.
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is it possible to assign the no of via for perticular net ??
hi,
i want to assign 10 via for every net is it possible to assign it ??how to assign it ??
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PSPICE - Text string problem
Hi all,
What I need to is define a text parameter, and compare it with another string.
below is my spice code:
.SUBCKT XXX 1 2
+ TEXT: Material_Name = "AL"
R 1 2 {IF(Material_Name=="AL", 100, 200)}
but the pspice compiler said:
**** EXPANSION OF SUBCIRCUIT X_R1 ****
ERROR(ORPSIM-15166): Bad expression
Material_Name is used as a PARAM here, but used as TEXT elsewhere.
ERROR(ORPSIM-15081): Can't add param <Material_Name>.
X_R1.R N00056 0 {IF(Material_Name=="AL", 100, 200)}
----------------$
ERROR(ORPSIM-16318): Missing or invalid expression
my question is, what is the correct syntax for comparing two string values...
thank in advance
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omit / ignore parts in a BOM(BOM_IGNORE?), also label as "do not stuff" automatically in BOM
I've looked at several forms/user guides/help documents and I'm unable to find the answers I'm looking for. I'm using orcad capture 16.2. I do *not* have CIS :'(
1. Is there a straightforward way to keep schematic compenonts off of the BOM. e.g. a PCB pad, fiducials, etc. EDIT: I'm aware there is a BOM_IGNORE property, but does this work on orcad captures BOM tool. Does it also affect the pcb editor properties? (BOM report,Component placement report...)
2. Is there a way to mark components as do not stuff so that when generating the BOM it will mark those components as such.
3. What is the preferred method for adding parts to the BOM that do not exist in the circuits but are part of the PCB assembly? e.g. heatsink. I read somewhere that making a library part with no pins is the way to go.
I'm looking for a way for the Bill of Materials tool to automate these for me. I want the BOM to output the "Item" "Qty" "Reference" "Part" and "Companies Part Number" fields such that I do not have to manually edit them whatsoever. Then I can add any other info from my own database such as RoHS status, description manufactures alternates etc.
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Power Pin Gray connection box
This is likely a stretch, but is there a way to force the power pins to display the gray connection box when they aren't connected? This would especially be useful with visible zero length power pins.
EDIT: a crude work around is to make the pin passive or simply other than power, but I'd like the pin to remain a power pin.
I'm using Orcad Capture 16.2.
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How do I add a drill to PCB
Hi !
Firstable i'm sorry, i'm a french student so that's why my english is not perfect...
I'm working on a PCB design and I'm trying to add drills to my Vias and Pins. I configured them in the Padstack Designer where I could see the drill hole. But when I update it to my design, there's no hole on my board and even less on my artworks... =\
I read a lot of threads here and on other forums but I did not find an answer. =(
Thanks.
I am using allegro 16.5.
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Allegro PCB Designer: 1 Unrouted net with 0 unconnected pins?
Hi,
I have a problem with a small design I'm working on. Under Display->Status I have 1 unrouted net with two unrouted connections, but when I check the unconnected pins report it shows 0 (see attachment).
- I have manually tried to find what I could have missed but have not found anything unrouted.
- I have dbdoctored the desig, still the same.
Could this be a bug or do I have some floaring trace or whatever lying around.
Best regards,
LMC
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Creating XNET's
How do I create XNET's in constraint manager for two nets with a resistor in the middle? Is it tied to the signal model for the resistor?
Thanks
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techfile in command
Hi all,
the "techfile in" command to display the "tech file in" dialog box.
I execute following script and this stopped by the "fillin" command.
Whyisthefillin '/ /Cadence/projects/4_Layer_tech.tcf"not accepted
version 16.5
setwindow pcb
trapsize 62499
generaledit
# Macro file: coordinates are relative to pick on replay.
techfile in
setwindow form.tech_in
FORM tech_in
FORM tech_in browse
fillin "//Cadence/projects/4_Layer_tech.tcf"
FORM tech_in execute
setwindow pcb
trapsize 62499
setwindow form.tech_in
FORM tech_in cancel
setwindow pcb
generaledit
Thx for help
Jürgen
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What is signal intergrity Analaysis? And where it is used?
Hi,
I heard that the analysis of Signal Integrity analysis. What does it mean, and at the PCB design where it is specifically it used.any tool we have to use it.
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Cant See Power nets
I am using allegro pcb design L (legacy). After successfully creating a netlist in capture and importing it in allegro, I cant seem to see the ratsnests for my GND and VCC power nets. I can successfully change the color of the pins connected to the power nets using the process of changing the color of ratsnests but the ratsnests do not appear. Is there something wrong with my capture schematic or is there an option where I need to turn on power ratsnests?
Thanks,
J
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Basic questions about Allegro PCB Editor
Hi all,
I am beginer of Allegro PCB editor, and have spent around one week's full time on it. Here are some question which have confused me. I would appreciate if you can help. The questions are based on the PCB figure in the attachment.
The 2-pin header footprint is made by myself. The procedure is following the standard one: padstack to define pads --> package symbol to define footprint. Here are questions:
(1) After I placed the 'Package Boundary' when designed the footprint, the footprint is covered by a net full of dots, as you can see in the figure. This looks really uncomfortable! Any one knows how to remove the dots in it? I have tried through 'Color/Visibility -- Stipple Patterns', and seems no help.
(2) As you can see, the font (size, line width) of pin number, device reference (H, HEADER) are the same, which also looks ugly. Is there any method to modify these fonts individually?
(3) There is a via above the footprint. It is just a 'Via' in default library without any further information. What I want to ask is: is there any method to define a via when I am layout, as is supported by all other tools? I know I can select a PRE-defined Via by padstack when layout, but is there any method to define a via just in PCB editor interface? PRE-define EVERY via I will use is terribly inconvenient, because in some complex PCB, there could be tens,even hundreds, of vias with different size. PRE-define them one by one in padstack is terrible to manage.
(4) In the Color/Visibility menu, there are tens of layer listed. However, most tutorials only talks about few of them, and left most of other layer unclear to me. Is there any document talking about this with more information?
I have went through the whole Allegro Layout Tutorial on the software, and I didn't get most of the information I want. Why it is called tutorial? It is not, definitely...
Thanks you all ~~
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Creating .PDF using Tcl/Tk Utilities in Capture 16.3
All,
Here's somthing a little different. I'd like to export a .pdf using the application found in Accesories--->Cadence Tcl/Tk utilites. This gizmo (when working) produces a searchable pdf which allows one to click on components within the pdf and see properties. I've seen this work in older versions of software. Here's the hitch; I need the postscript driver path for the .pdf editor Bluebeam. I can also use the postscript friver path for Adobe Acrobat Distiller but I prefer to use Bluebeam. Attached is a .png that shows you what I am refering to. Any info will be appreciated.
Cheers,
Ron Scott
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problem in capture cis ICA
hi;
when i found a part in capture cis by using internet component assistanf, i got a messagebox
said "Cannot place part outside of Capture CIS" ,my computer is win7 64bit,is anyone else got
this problem?
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I had doubt on Micro strip Interconnect ?
Hi,
I had started to learn the Sig Explorer on cadence. I had an idea on the losses and other terminology used in the signal analysis. I had simulated an basic RLC network with the IO pulse as Input and IO tristate as Output side and intermediately the Dummy Probe had kept and the losses calculated.
But When i want to simulate the RLC network with far network and near network, i had inserted the micro strip in between the two networks. An sample tuto had explained some of the things with micro strip, but my question is in case of any micro strip is inserted the losses at the output side will be more or less?
Then micro strip parameters are represented as Impedance and PropDelay, trace geometry , velocity.
What is the prop delay and Velocity?
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cadence orcad 16.3 error
hi,
Can´t select A/D analog or mixed, in file -> new ->project.
Can´t run the circuit.
can´t measure corrent and voltage.
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PSPICEONLY field
Hello,
We use Orcad Capture for a while and we had in our components a field named 'PSPICEONLY' : when set to true, our component doesn't appear in the netlist, but stay in the BOM. We also used another field : 'BOM_IGNORE', to set if the component will appear or not in the BOM.
But it seems that there is an 'innovation' on the recent versions of Orcad Capture (maybe since the 16.3 ?). The fields doesn't seem to have the same use : 'PSPICEONLY' set to true ignores the component in the netlist AND in the BOM, and 'BOM_IGNORE' doesn't seem to work anymore.
Despite the fact that we have to rework all our librairies, is there now a field that can have the same functionnality than the old 'PSPICEONLY' field, namely that the component has to appear in the BOM but NOT in the netlist.
Thanks,
Jérôme
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How to connect vias to specific layers
I have a design which has 7 layers. The top layer has only short stubs.
There are two layers for traces but they are sensitive signals and there is a solid ground plane above and below these two layers. I have connected these two planes at one point near the incoming supply. I also have a single ground plane as layer 7 which is noisy.
How do I connect a number of ground signals from Layer 1 to Layer 7 WITHOUT connecting to the other two ground planes, which would inject noise onto these planes?
When I try using the normal vias, they connect all planes from 1 to 7 and also 2 and 5, I just need layers 1 and 7 connected but they need to connect at the supply (one via connecting layers 1, 2, 5 and 7).
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