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Orcad Capture TCL scripting

May 2, 2010, 12:26 pm
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Hi All,

I would like to use Orcad Capture TCL scripting. Before the 1st hotfix of 16.3 the command window in Capture echoed all of the operations performed during the editing session. Also .captcl session script log file was available as it is written in the manual. Since 1st and till the 7th hotfix neither command window echo nor .captcl session script log fileare available, and this was my ultimate source of examples.

What can be done to get both features back? (Apart from uninstalling all of the hotfixes.)

BTW, I use Win7/64 and tried to run Capture as administrator, if this info may help.

Best Regards,

Azef.

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Which text will be printed on PCB?

December 12, 2013, 10:32 am
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Dear all,  I have two questions, anyone can help me? Thanks a lot!

(1) There are text on "Autosilk_top", also there are text of " RefDes" on "Silkscreen_top" of the component, which text will be pritned on PCB board after manufacture?   Or both?

(2), Which layer of the boundary/outline of a component (e.g. the circle of a through hole capaciatance) belong to?  When I turn on or off the "silkscreen_top" of the component, it is still displayed, seems it doesn't belong to silkcreen layer.  

 Thank you very much!

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Problem in accesing to PCB edit tools of Allegro 16.5

December 13, 2013, 1:22 am
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I use Allegro16.5 under linux but today I can't access to PCB edit section. When I click on "Layer" or "PCB symbol Editor" icon in Allegro PCB Librarian, nothing happens! and on statusbar it shows "Exiting ... $CDS_INST_DIR/tools/fet/bin/LibFlow".

What is the problem? how can i fix it?

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Configuration/ Revision/ Version Control of Design files

December 13, 2013, 12:07 am
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Normal 0 false false false EN-GB X-NONE X-NONE MicrosoftInternetExplorer4

Hi,

I was wondering if anyone would like to share how they manage revision control over their schematic, layout and associated files when using Concept-HDL (schematics) and Allegro?

From a web search I see there is an option to link in with PDMLink from a 3rd party company Windchill, which may be option for us as our Mechanical department use this tool. However, it's not common across our company. Ideally a free open source revision control process would be best, like subversion. (We have done some initial study on this, but does not look too easy to integrate with Cadence)

 Additionally, our problem is thinking about what files need to be under version control? I.e. what are the minimum number of files required to bring a design back to life in the event of data corruption? There appears to be many sub folders and files created as part of an overall schematic and layout design. (I have asked Cadence about this, but no clear answer comes back!)

We could of course just zip the whole design and put that into subversion (or similar), however, in the true spirit of revision control this is not really an answer. (I used Altium in the past, and it worked without any issues in Subversion. You could change multiple schematic page files, and easily roll back to an earlier version of just one of them then re-sync with PCB, only update files that changed, etc..... this is what a true revision control system should give a user)

Any advice on how others are currently achieving this will be of great interest.

Many Thanks

Colin

/* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:"Times New Roman"; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin;}
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Step files in Orcad PCB Pro 16.6

December 11, 2013, 1:16 pm
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Hi,

Im trying to use step files in Orcad 16.6 but the option doesnt seem to be anywhere. The videos I have watched show enabling the option in "User Preferences > Unsupported" but there is no option to enable it. The step folder path is not listed under paths either. The menu option to open up the step files also isnt avaliable.

Can anyone tell me know where I can find the option to enable this or how to use it?

 Thanks 

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Cadence 16.6 database corruption

December 13, 2013, 7:41 am
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Hi there,

I received this message "Database has a non-recoverable corruption...." when it was trying to import netlist into Allegro. I checked my footprints and they were ok then re-ran netlists then it kept giving me the same warnings. Please help! Thanks.

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Netlist error

November 16, 2013, 9:09 am
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I created my connector footprint by using the "CONN RCPT 46X2" model from the library then I renamed it as 123456.dra and put it in my project folder. When I created the Netlist and the error was listed in the netrev file as Porblems with the name of device 'CONN RCPT 46X2_123456_CONN RCPT 46X2': Name is too long.'

I tried to look under its property and the 123456 was listed under footprint column correct. I didn't know where else I can change its name or to look for! Can someone please help?

Thanks so much!

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مشاهدة مباراة الاهلي و جوانزو ايفرجراند الصيني 14-12-2013

December 14, 2013, 6:58 am
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is it possible to highlight the dummy pins ??

December 15, 2013, 11:24 pm
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Hi everyone,

is it possible to high light the dummy pins for perticular components ??

is it possible to explain the Topology ?? (Daisy chain ,T-point ,star topolpogy )

where it will be use  ??

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I had doubt on Micro strip Interconnect ?

December 10, 2013, 1:28 am
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Hi,

I had started to learn the Sig Explorer on cadence. I had an idea on the losses and other terminology used in the signal analysis. I had simulated an basic RLC network with the IO pulse as Input and IO tristate as Output side and intermediately the Dummy Probe had kept and the losses calculated.

But When i want to simulate the RLC network with far network and near network, i had inserted the micro strip in between the two networks. An sample tuto had explained some of the things with micro strip, but my question is in case of any micro strip is inserted the losses at the output side will be more or less?

Then micro strip parameters are represented as Impedance and PropDelay, trace geometry , velocity.

What is the prop delay and Velocity?

 

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Can you modify OrCAD BOM Header Info?

December 17, 2013, 9:02 am
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 This question is about generating a BOM using the Tools->BOM command in OrCAD CIS 16.6. When you generate this BOM, OrCAD adds some header info at the top like board name, date, revision, company & address, etc. Is there anyway to modify or create a custom template of what header info OrCAD attaches to the top of the BOM report? Thanks.

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Error in script generated by Ultra Librarian

December 17, 2013, 11:25 am
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Hi all,

First off, I have never writtens script of my own but I just recently discovered Ultra Librarian (http://www.accelerated-designs.com/ultra-librarian/) via a post on this forum. The script it generates for specific component fails on a certain line of code below. 

The component is: Atmel AT32UC3B0256-A2UT

Footprint is: TQFP64-4

The line that it fails on is line 1902 of the .scr file in the link below: "setwindow Form.editprop1". I have tried doing a google search for the command setwindow but there are few results. Maybe there is some type of scripting manaul for PCB Editor I am unaware of?

Error message the PCB Editor outputs when line 1902 is executed: "E- Can't find window; Form.editprop1". Maybe that window isn't opened so it fails?

Cadence version is: 16.6 S020 (v16-6112BH)

Does anyone have any recommendations?

Link to files that Ultra Librarian creates: https://drive.google.com/file/d/0B2GLtRsUI-2bYVRKS2NQSEpuaXM/edit?usp=sharing

Thanks, Aric 

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Experiences in PCB Design Flows

November 18, 2013, 6:32 pm
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Hello everyone,

 

I would like to get some advice from experienced users (professionals or regulars) in PCB Design flow, especially in complex PCB boards.

I already made PCBs, following the "basic" design flow as shown in this picture :

 

 

But now I'm starting to make larger PCBs which are more complex, and I have some questions in the PCB Design step (red rectangle of the previous picture), especially in the "Trace Routing".

For example, I draw the schematics of a complex board and do the simulations, then I design the Layout to finally have something like this :

 

 

And I wonder to know the "Correct Flow" to design the layout correctly :

After placing the components, should I start with routing the "signals nets", and then routing the "Power nets VCC_5V, VCC_3.3V, ...", and finally do a ground plane with all GNDs ?

Or is it necessary to route all the nets at the same time, hoping having something correct ? 

 

Thanks for your help !

 

Yoann 

 

 

 

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PDF Export successful but no file generated

December 18, 2013, 2:10 pm
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Im using the Tcl/Tk unitility to export an intelligent pdf of my schematic. (Allegro Design Entry CIS 16.6 on Windows7 64 bit)

I've got all the paths set correctly

Postscript Drier:PDFCreator
PS to PDF Converter Ghostscript  

Windows pop up during the coversion.  The first ones are too fast to read but I assume they are the conversion to postscript.  Then a second window pops up saying "Printing file on the and the PDFCreator on PDFCreator Page #"  where # increments.  The utility finishes successfully. However when I look in my destination folder there is no pdf there.   

Any idea what is going on?  I've copied my output log below.  

 

(::capPdfUtil::printPdf) Output Directory : N:/Electronics/dtra3_array/dtra3_array_ver3 Output File : DTRA3_ARRAY_VER3.pdf
(::capPdfUtil::printPdf) Annotating page objects for SCHEMATIC2 : CONNECTOR
(::capPdfUtil::printPdf) Annotating page objects for SCHEMATIC2 : SOLOMON READOUT
(::capPdfUtil::printPdf) Annotating page objects for SCHEMATIC2 : VOLTAGE REFERENCES
(::capPdfUtil::printPdf) Annotating page objects for SCHEMATIC2 : XCHIP_READOUT
(::capPdfUtil::printPdf) Annotating page objects for SOLOMONWIRE : SOLOMONWIRE
(::capPdfUtil::printPdf) Annotating page objects for SOLOMONWIRE : SOLOMONWIRE
(::capPdfUtil::printPdf) Annotating page objects for SOLOMONWIRE : SOLOMONWIRE
(::capPdfUtil::printPdf) Annotating page objects for XCHIP1 : XCHIP1
(::capPdfUtil::printPdf) Annotating page objects for XCHIP1 : XCHIP1
(::capPdfUtil::printPdf) Annotating page objects for XCHIP1 : XCHIP1
(::capPdfUtil::printPdf) Annotating page objects for XCHIP1 : XCHIP1
(::capPdfUtil::printPdf) Annotating page objects for XCHIP1 : XCHIP1
(::capPdfUtil::printPdf) Generating PDF file from postscript ....
(::capPdfUtil::printPdf) Successful

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Orcad PCB / Allegro version conversions? (Argh!)

December 18, 2013, 5:44 pm
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I know; I should rob a bank and get my 16.2 Orcad PCB upgraded. But I don't really want to develop criminal skills. So I've spend a few days trying to find some way to convert 16.3 (and later) libs and boards to 16.2. And came up with absolutely nothing but a nasty feeling that Cadence is doing this primarily to annoy me enough to push me into a bank robbery, a newer, cracked Orcad or other unethical/illegal ventures?!?

However, I still hope someone out there has found a solution? In my humble opinion it just do not seem right that there's no converters available - or even documentation to allow someone to develop one?

Merry Christmas to everybody!

PS: It even seems my 16.2 is only able to save to one other version (16.01) - that also seems a bit pathetic as the formats seem to change with almost every version?

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typical Allegro learning curve ?

February 9, 2010, 12:19 am
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We are seriously considering moving from Pads-PCB to Allegro due to increasing signal integrity and density issues,

Has anyone had a similar conversion in the recent past, or have any ballpark figures on the duration of the learning curve.

We have three PCB designers, each with 15+ years as designers. We know that as soon as we upgrade we will be asked how soon the new boards are going out. Sound familiar?

All inputs will be graciously appreciated.

 thx... Jeff

 

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Library Managment in Allegro V16.5 & Browsing Packaged Symbols.

February 7, 2013, 7:51 pm
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I was wondering is there a way to segregate out Package Symbols in their own directory by function and have those package symbols show up in the placement menu "segregated out" instead of just a huge list of all of the packaged symbols.For example I have a folders called THPARTS, SMDPARTS,CONNECTORS each of these folders contain packaged symbols but when I check the library check-box in the placement menu and then select the packaged symbols all of the parts show, so it is just a huge jumble of all parts from all of the libraries.

I just want to be able to browse packaged symbols by function, is there a way to do this ? or by the folder name so it is easier to see whats what.

Thanks Guys... Scott
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How to place via arrays in a dynamic shape?

December 19, 2013, 11:04 am
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Any one can help me to place via arrays in a dynamic shape?

Using menu "Via arrays"->"Matrix" and select "Shape mode", it doesn't work, however, it works in "Board mode" or "Area mode", but I only want to play via arrays on Shape, not on the whole board.

It says"  Enter a point or a box.
W- Xtalk table in drawing board.brd does not exist. For xtalk estimation or xtalk DRC update, xtalk tables must be generated."

Thank you very much!

 

 

 

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How to add additional delimiter in BOM - HDL?

December 19, 2013, 6:24 pm
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Hi,

         How can I add additional delimiter in BOM - HDL?  The delimiter present in my BOM - HDL are COMMA, SEMICOLON, COLON, SPACE, DOT, HASH # and TAB.  But on my colleague's pc, there is no TAB delimiter.  How can I add TAB delimiter in his pc?  By the way, we are using the same license.

Thanks,

Mabel

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Text to Hole Constraint

December 19, 2013, 2:24 pm
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Hi All

 I've created some text using Etch in a inner layer, and I've a VIA with supressed pad (basically just a drill hole) through that inner layer. Somehow the drill hole is stacking the text and it doesn't give me DRC flag. Anything I can do to flag this kind of error? Constraint manager?

 

thanks!

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