Step models for PCB footprints

December 19, 2013, 6:12 am

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Hello

We are considering adding 3D step models to our PCB footprints.

Where does one find these 3D models in order to do this?

I found a place on the web that has 3D models for download but they have a different file extension than .stp.

I downloaded one and tried to map to an existing PCB footprint but the step molel packager didn't see the model extension .skp that it was created in.

I know of a 3rd party software program avaliable to help do this but not everyone will be able to afford to purchase it.

Any ideas on how to accomplish this?

Thanks,

Carvey

 

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Is there a dedicated Concept HDL forum?

December 18, 2013, 3:18 pm

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Does anybody know whether there is a dedicated Concept HDL forum or not?

 Thanks,

SKILL script to create symbol origin marker

November 1, 2013, 11:53 am

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 Anybody have a SKILL script that will make a small circle with crosshairs, at the symbol origin on PACKAGE GEOMETRY/BODY_CENTER, that will run from inside the symbol editor?

PCB Editor

December 20, 2013, 1:52 pm

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I have been using OrCAD PCB Editor for a short time and haven't really had any major problem. One thing that is very annoying is that when I am moving parts or text on the layout the curser jumps up to the right top corner when I select a part or text. This also makes the board shift to the left a short distance. It seem that there should be a setting that either enables or disables the curser to jump up to the visibility tools or something.

Please help. 

Model Editor - Can't "Extract model"

December 21, 2013, 7:43 am

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Hello all!

I have opened with Pspice Model Editor Demo a .lib library of an IGBT  that I downloaded from a manufacturer and the option "View-> Extract Model" is not enabled. Is it because the model is somehow “protected” by the manufacturer or is it because I’m using the “Demo” version?? I couldn’t find any explicit mention to it in the “OrCAD Lite Products Reference”

And while I’m at it, if I understand it correctly, a .lib file contains the same instructions as a netlist file. Then my question is: Is it possible to display a schematic out of a .lib file? It would help me a lot to visually see the model I’m using, instead of reading the .lib file…

Normal 0 21 false false false DE X-NONE X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Normale Tabelle"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin-top:0cm; mso-para-margin-right:0cm; mso-para-margin-bottom:10.0pt; mso-para-margin-left:0cm; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;}

CIS Schematic Page numbering

December 20, 2013, 11:45 am

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I would like to have the page numbering in my schematics title block automatically update with the correct page numbers.  For example, let's say I have a 50 page schematic and I would like to have my title block automatically update with the text "SHEET X OF 50".  I would like the "X" to be automatically replaced with the correct unique sheet number and have "50" automatically appear on every sheet.  Also, I would like to type my drawing number in only once and have it appear on every sheet "DWG NO: ABC-123".  I would like to have ABC-123 appear on every sheet.  Any help would be appreciated.

I had doubt on Micro strip Interconnect ?

December 10, 2013, 1:28 am

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Hi,

I had started to learn the Sig Explorer on cadence. I had an idea on the losses and other terminology used in the signal analysis. I had simulated an basic RLC network with the IO pulse as Input and IO tristate as Output side and intermediately the Dummy Probe had kept and the losses calculated.

But When i want to simulate the RLC network with far network and near network, i had inserted the micro strip in between the two networks. An sample tuto had explained some of the things with micro strip, but my question is in case of any micro strip is inserted the losses at the output side will be more or less?

Then micro strip parameters are represented as Impedance and PropDelay, trace geometry , velocity.

What is the prop delay and Velocity?

 

Allegro display qusestions

December 23, 2013, 4:43 pm

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 Hi All,

 I have some basic questions about the display of allegro, as you can see from the attached figure 1,2, and 3.

In figure 1, you cans see the three RED pads in the same net. The top and the bottom ones seem to have some stipple pattern on it, but the middle one doesn't.

In figure 2, the nets of 3.3V, GND, and some of my signal (BLK), are in grey color, which make it harder to differentiate their layer.

In figure 3, the routing of net BLK are in a color of grey and red, which looks strange.

 What I am wondering is how to make these color uniform? I mean, all the pads, trace on the top layer are all in a single color, for example, red. I don't want the grey color, and neither the stipple one.

 Btw, I didn't set any stipple pattern in Color/Visibility, and set the pads and routes in the top layer in RED. but the final PCB seems strange...  

I would appreciate your help. Thanks~~

  

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Need Help, Orcad Capture and Pspice simulating

December 24, 2013, 1:27 pm

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I simulated 

* source TRIAL

X_M1         -1 0 MEMRISTOR PARAMS: RON=10K ROFF=100K RINIT=130K D=10N UV=10F

+  P=1

R_R1         -1 0  1k TC=0,0 

V_V1         -1 0  

+SIN 0V 0.1V 0.56Hz 0 0 0

 with the the memristor code

 .SUBCKT memristor Plus Minus PARAMS: 

+ Ron=10K Roff=100K Rinit=130K D=10N uv=10F p=1

***********************************************

* DIFFERENTIAL EQUATION MODELING *

***********************************************

Gx 0 x value={ I(Emem)*uv*Ron/D^2*f(V(x),p)}

Cx x 0 1 IC={(Roff-Rinit)/(Roff-Ron)}

Raux x 0 1T

* RESISTIVE PORT OF THE MEMRISTOR *

*******************************

Emem plus aux value={-I(Emem)*V(x)*(Roff-Ron)}

Roff aux minus {Roff}

***********************************************

*Flux computation*

***********************************************

Eflux flux 0 value={SDT(V(plus,minus))}

***********************************************

*Charge computation*

***********************************************

Echarge charge 0 value={SDT(I(Emem))}

***********************************************

* WINDOW FUNCTIONS

* FOR NONLINEAR DRIFT MODELING *

***********************************************

*window function, according to Joglekar

.func f(x,p)={1-(2*x-1)^(2*p)}

*proposed window function 

;.func f(x,i,p)={1-(x-stp(-i))^(2*p)}

.ENDS memristor

 

and I created a new simulation AC sweep profile  .AC DEC 10 0 10000

and i get the error

ERROR-- INVALID VALUE

.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))

.INC "..\SCHEMATIC1.net" 

 

and I donot know what to do?

So please can anyone help me... 

Gerber creation

December 19, 2012, 8:44 pm

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 Hi All,

I have a problem of gerber creation. The details are,

1. Assume I have XYZ design file for which I need to create gerber. But it's not happening.

2. But for any other design file I can create gerber except above XYZ file  .

Please help me....

Attaching Different Nets

April 27, 2010, 10:26 pm

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Greetings,

 

    I have a design where I need to connect nets of different names. While I've done this many times, there's a hitch in this design. My boss is very uncomfortable with my present method of combing nets because it take an interaction with the board shop to make my intention clear. I create a different layer and I call it ADD_ETCH and it is laid across the gap to connect two different nets. This does not create a DRC in the layout but when implemented at the board facility it will create a DRC. Of course, when the board is in CAM, I will get a phone call (every time) to confirm my intent. I now have to come up with a method to have the connection show up when viewed with an external Gerber tool.

    The way I intend to approach this is wait until the design is almost near completion and change both nets to STATIC SOLID vice DYNAMIC SHAPE. I will then drop a polygon of appropriate dimensions across the gap(layers of concern are internal). I am presuming this will cause a DRC. My questions are:

 

1) Is this method reliable?

2) Changing from one shape type to another will not change the attributes of either shape, correct? For example, if I have a net named GND and the other is GND_PWR, the layers that these net names are assigned to retain their original names, correct?

 

This exercise is to be able to see a physical connection when viewed by a typical gerb tool. Any advice or clarification will be greatly appreciated. Referrals to specific literature would be useful also. Thanks.

 

Cheers,

Ron Scott CID+

How to Pass Shorted Nets from Schematic to PCB Board

December 25, 2013, 9:31 pm

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Hi guys, I'm dealing with many projects with the following situation: I need to short different types of net together while they go to the same pin. (not only force/sense)

 

You can see from the picture above that TM_1_S0 is shorted with 01F_S0. It's common practice that we use a 'tie' to short them in DE HDL. But after we export physical to PCB board, there will only be one net name left for both of the original nets.

 

This might caus potential risk if we have different routing constraints like width, layer, impedance control, etc. for these two nets.

 

I wonder if there is any good way to separate them clearly in both shematic and PCB layout stages.

 

I  searched Cadence help files and found a document inllustrating Kelvin connection. But I'm using a SPB 16.3 version while it's 16.5. Could anyone offer a SPB16.3 version, I remember the Kelvin connection symol is different in SPB 16.3.

 

Thanks and Merry Xmas! 

مشاهدة مباراة الاهلي و جوانزو ايفرجراند الصيني 14-12-2013

December 14, 2013, 6:58 am

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Gerber files

March 31, 2007, 11:34 am

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Hi, I am trying to create output files of my PCB design for manufacturing. I am having trouble figuring out how to create files for the soldermask and copper layers. Under artwork, I created .ART files. I feel like this is what I need for the copper layers. Am I right? If that's the case all I need to know is how to create the files for the soldermask. Thanks for any help.

Originally posted in cdnusers.org byfongcj.eee

[Need Help]Cadence16.6 Entry point not found, could not be located in the dynamic link library ordb_dll.dll

December 27, 2013, 12:47 am

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Install cadence 16.6 ok, but fails to open the exe.

Capture fails is just as the picture. 

Allegro also fails, says could not be located in the dynamic link library cdscommon.dll. See the pic.

 I used to install cadence16.3 and pads9.3, but before the installation of 16.6, I uninstall these two softwares.

 After the failure, I reinstalled 16.6 for 2 times, all the same symptom.

 

I moved the CDSROOT information to the front of "PATH" in the environment variables, no effect. My computer is XP SP3. 

I work at Freescale, we use the company dynamic license. 

 

Thanks! 

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ORCAP-1228: Part is out of date with design cache but cannot update cache to resolve.

December 30, 2013, 2:04 pm

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When adding a part to a schematic, I sometimes get the error:

ERROR(ORCAP-1228): Part <part name> is out of date with respect to the design cache. Use Update Cache to synchronize the part in the cache with the library. 

Where <part name> shows the name of the part I am trying to place. This seems to happen only when my database (I am using CIS) points to a symbol in a specific library - the MASTER_IC library. Other parts in the same database table, but pointing to a different schematic library, work fine.

After dismissing the error, the part will be placed. However if I place a different part that also has this problem, then try to place the first symbol again, it will not place the part even when dismissing the error. This time I will also get ORCIS-6184, and I cannot place the part.

What could be wrong with my MASTER_IC library causing this problem? If not a problem with the library, what could the problem be?

The error message says to update cache, but this does not help. This happens even when a completely blank design with nothing in the cache so I do not see how the part could really be out of date with a fresh design cache in the first place. 

problems opening STEP file in solidworks

August 29, 2013, 8:54 am

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I am trying to open a PCB STEP file in Solidworks 2012 SP05. I am running SPB 16.6 so15 latest hotfix.

When I export from allegro in AP-203, Solidworks tells me "The file being read in is not a AP203 or AP214 file. Do you wish to continue?" I select yes...Solidworks crashes.

When I export from allegro in AP214, Solidworks proceeds to open the file with no warnings.....and then crashes.

When I export from allegro in AP242, Solidworks tells me "The file being read in is not a AP203 or AP214 file. Do you wish to continue?" I select yes...Solidworks crashes. Solidworks 2012 SP05 doesn't appear to recognize the AP242 format in the list of FILE>OPEN options.

Anyone else having these issues? Could this be an issue with my computer?

FYI, I am on the hairy low edge of even being able to do any 3-D modeling. Video card has 256mb memory, XP 32bit system, 2gb ram.

 

[Help] PADS layout to Allegro PCB translation

January 3, 2014, 2:15 pm

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Hi all,

First, thanks for the time of you on this post.

I have a 8-layer PADS PCB layout designed by other people, which you can see from the attached Figure 1. What I want to do now is to extract the footprints of components in the PADS board layout to Allegro, so I don't need to redraw the footprint of some component. I have done some homework on the procedure, which is explained below, but still can't get it done.

The version of the PADS software is 9.5. The Allegro version is 16.6.

1: First, export the PADS PCB layout into .sci format. The settings is in attached Figure 2. Is it correct?

2: Copy the default pads_in.ini file to my directory. The contents of this file is listed in Figure 3. But I don't know how to modify it based on my case.

3: Launch in Allegro that File-->Import-->CAD Translator-->PADS, choose the .asc and .ini file, and run Translate.

I get some errors here, which is listed below:

Using translator version @(#)$CDS: pads_in.exe v16-6-112X 3/11/2013 Copyr 2013 CADENCE DESIGN SYSTEMS.

Reading PADS ASCII file header.

PARSE ERROR: Unrecognized format in header line of input file.

Line 1: !PADS-POWERPCB-V9.5-BASIC! DESIGN DATABASE ASCII FILE 1.0

ERROR: Finished with errors.

 

 

 

Simulation Profile Setup Issues

December 4, 2010, 6:52 pm

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Hey I'm pretty new to PSPICE and I've followed every tutorial there is and they all pretty much say you can choose the "none" option to avoid the inherit from issue when there are no .sim files to inherit from. I have Orcad_lite_9_2 and I'm in the"PSPICE AD Lite Edition" and I went to New Simulation Profile and I see the fields for "Profile name" and "Inherit from existing profile" as well as the "Create" "cancel" "help" and even "..."(browse) buttons but I don't see a "none" option anywhere. I've searched for hours and I've got a project I have to get finished.

No Pspice Design Template for IRF150 in Orcad Lite 16.6?

January 6, 2014, 7:52 am

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Hello all, I'm trying to simulate a circuit with an IRF150 (from the EVAL library) in Orcad Lite 16.6 and when I create the netlist I receive the warning "WARNING(ORNET-1119): No PSpiceTemplate for M1, ignoring", M1 being the IRF15. Does that means that the IRF150 is not supportedanymore in the LITE version? If I recall correctly with PSpice 9.2 it was included.

Many thanks in advance

Cheers!