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How to use the some set of vias under the top to bottom layers?

July 13, 2014, 8:42 pm
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Hi.. For the specific board design the top and bottom layers should been get connected set of arrays.For that option i had tried to use the thieving parameters. In that rectangle type shape has enabled to use it. but when i am try to use other shaped it is not possible. Suppose if try to put the vias thieving parameters,In case i want to increase the pad size of via directly means the how is it possible? Can i edit the via pad stack in the thieving parameters. Thanks & Regards Dhamodharan
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OrCAD16.6 DRC Error: ERROR(ORCAP-2207): Check Bus width mismatch

July 14, 2014, 1:04 am
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Hi,

When I run DRC. I receive below message at the end of report file, although I checked the whole design completely:

Checking Misleading Tap connection
ERROR(ORCAP-2207): Check Bus width mismatch
Checking Physical Rules

I googled and found out this bug has been fixed in Capture16.6 QIR. What should I do now? Can I safely ignore this message or there is still something wrong with my design that I should correct it? Where can I find  and install thehotfix for it?

I would appreciate any help on this issue

Hossein

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Allegro Design Entry CIS - "Select entire net does not work on separate pages"

July 13, 2014, 11:50 pm
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Hi all,

I don't know what happened  or i did somethings wrong on my schematic.

I previously could select a net that was connected by off-page in 2 pages in 1 schematic by "select entire net" then the net was hilighted (both in 2 pages).

In what way or somehow, now when i do the same excute above, the net just hilighted in one page only. 

I also tried to reboot laptop but nothing better.

This makes me really confused. please help me out if you guys knowledge on this.

 Thanks,

TDP. 

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Routing on top and bottom side is possible with any option on etch???

July 14, 2014, 2:39 am
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Hi..

I had worked on the pcb with two layer board. In old days worked with the layout i use to route the enabled ratsnest on top side, at connection tool----> make and connection between source to destination with connection tool.. Then put the route by bottom on the connection enabled by tool.                       Still my doubt is i had put the etch(top) on my board and then if need to try route the etch on bottom side means how it is possible.

Can any provide any solution for this.      

Thanks & regards  Dhamodharan
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DRC & Create Netlist Error(ORCAP-36041): Duplicate Pin Name. Please renumber one of these.

July 14, 2014, 4:43 am
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Hi,

I have created many parts in OrCAD which have 'NC' pins - or other pins with similar names: IO,.. - when I run DRC or create netlist I see below error messages in the DRC report file or session log:

#2 ERROR(ORCAP-36041): Duplicate Pin Name "NC" found on Package xc6slx45fgg484F , U22F Pin Number P15: SCHEMATIC1, 10-FPGA Power (0.00, 0.00). Please renumber one of these.
#3 ERROR(ORCAP-36041): Duplicate Pin Name "NC" found on Package xc6slx45fgg484F , U22F Pin Number D12: SCHEMATIC1, 10-FPGA Power (0.00, 0.00). Please renumber one of these.
#4 ERROR(ORCAP-36041): Duplicate Pin Name "NC" found on Package xc6slx45fgg484F , U22F Pin Number E10: SCHEMATIC1, 10-FPGA Power (0.00, 0.00). Please renumber one of these.

My device has really lots of NC pins: accordingly, I have made my schematic parts. However, I see lots of errors when running DRC or creating Netlist!.

I should add that 'NC' pins are defined PASSIVE.

I appreciate any help on this issue.

Hossein

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OrCAD16.6 DRC check problem: "Net has two or more aliases"

July 14, 2014, 12:33 am
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Hi,

I have used net names of my power symbols for various pins. Running DRC I see below messages. How can I get rid of such messaes?

INFO(ORCAP-2212): Check Power Ground Mismatch
QUESTION(ORCAP-1589): Net has two or more aliases - possible short? U18,PVIN  PVIN  DDR1V8
                    SCHEMATIC1, 05-DDR2 & GP Flash  (106.68, 185.42)
QUESTION(ORCAP-1589): Net has two or more aliases - possible short? U18,VDDQ  VDDQ  DDR1V8
                    SCHEMATIC1, 05-DDR2 & GP Flash  (106.68, 175.26)
QUESTION(ORCAP-1589): Net has two or more aliases - possible short? U16,VDD  VDD  DDR1V8
                    SCHEMATIC1, 05-DDR2 & GP Flash  (241.30, 22.86)
QUESTION(ORCAP-1589): Net has two or more aliases - possible short? U16,VDD  VDD  DDR1V8
                    SCHEMATIC1, 05-DDR2 & GP Flash  (243.84, 22.86)

Any comment would be appreciated.

Thanks in advance,

Hossein

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Assign Pattern option ( disable or a way to set it )

July 3, 2014, 9:16 am
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 I am using the funckey "code below" and now with v16.5 a "Assign Pattern" window is popping up.   I am trying to either set the pattern or disable it completely so my "F" key is more effective.

 Thanks in advance for the reply :)

 

funckey F "generaledit; prepopup ; pop dyn_option_select 'Selection set@:@Clear all selections' ; set prompt ; prompt 'Enter Ref Des (on next step click pattern to keep it highlighted' ; refdes $prompt ; zoom selection; hilight  ;generaledit "

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Does IBIS to Pspice Converter Work in ORCAD Lite 16.6.S022?

July 14, 2014, 10:05 am
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Hello, I tried converting an IBIS Ver3.2 model from Texas Instruments using ORCAD LITE 16.6; and I get the following error message in my ibis2spice.log file: ERROR: in launching Ibis2signoise.  Any ideas on what the problem might be?  I followed the on-line help for doing the conversion.  These are the steps that I followed: 1) started up Model Editor (run as administrator-Windows7-PRO-64bit)  2)Begin a new model FILE-->NEW  3)Begin an IBIS translation MODEL-->IBIS_Translator...  4)Load in my ibis file  Browse/my.ibis  5) tried clicking one-check box (make model names unique)  also tried checking both boxes (+ always regenerate.dml)  got same failure for both cases.  6) hit okay to continue. Result, popup box says IBIStoPSPICE Error; Errors during IBIS parsing. Please see ibit2spice.log for details. 
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Library Conversion form layout to editor is possible?

July 14, 2014, 8:35 pm
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Hi.. I had maintained some of the power modules in layout 9.2 version. But when i am try to use it for the editor is possible. Any import option is possible from .llb to .dra conversion. No i am using OrCAD 16.5 with pcb editor. Any possible is solutions will more appreciated. Thanks & regards Dhamodharan
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Global Schematic Page Properties, Page Size change for Existing Design in Allegro Design Entry CIS (Cadence 16.6)

July 17, 2014, 3:18 am
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Hi,

I've Schematic design with more than 100 pages, how to increase the page size globally for all pages instead of doing it sheet by sheet.

Please help to update. EDA Tool using: "Allegro Design Entry CIS (Cadence 16.6)"

Thanks in Advance.

Regards,

Bala

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How to use the thieving parameter in pcb?

July 16, 2014, 9:03 pm
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I had worked on the pcb, but when i am try to put the set of free vias, i had used the parameter of theiving. When i am try to use it, that has been get enabled for single layer.How to use the parameter? Thanks & regards Dhamodharan
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Footprint not showed

July 17, 2014, 7:59 am
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 Hello. I'm using orcad 10.3. I made a footprint, but when it is placed in my PCB design it is invisible. There is nothing in the silk screen layer for this footprint. I can see the drill symbols and the solder mask areas. I need the content of the silk screen layer because it has some mounting-hole marks for a heat sink. Any idea about where the problem could be.?

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funckey

July 17, 2014, 10:41 am
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I want to use the keypad home/left arrow etc with funckey.

Is there a list of what these keys are called?

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Footprint viewer in Capture schematic

July 17, 2014, 11:57 am
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 Hi

I just got a new computer and a new install for 16.6 software program.

Having trouble setting up the above to view footprints in schematic capture.

In PCB EDITOR user preferences I have set the paths to my symbol libraries.

In my capture.ini file I have the following entry;

[Allegro Pootprints]

Dir0=P:\a_PCB_Design\CADENCE PCB DESIGN\SYMBOLS\CAPS

If I select a cap in the schematic file and RMB, show footprint, I get the following error message;

Could not find padstack.... Cannot open the design database file, unable to open CAP0603.psm

I have read many posts on this topic but still unable to figure it out.

Thanks,

Carvey 

 

 

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Is Bold Text Possible?

July 17, 2014, 12:38 pm
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I know how to change my text, Edit > Change, and then use the options menu on the left. But, I don't know how to change the style of the text. I don't mind the font necessarily, but I want large, bold text but as far as I can tell size 13 is the largest and the font itself is very thin.

I was also wondering why the "text block" size is not linear? It seems to go up to 40 something, yet as far as I can tell size 13 is the largest with 12 and 14 being smaller.

Changing the line width doesn't do anything either, my command window just says "Text already matches option panel settings". 

I've searched other posts and haven't seen anything similar to this, 

Can anyone help? 

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Orcad Capture TCL scripting

May 2, 2010, 12:26 pm
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Hi All,

I would like to use Orcad Capture TCL scripting. Before the 1st hotfix of 16.3 the command window in Capture echoed all of the operations performed during the editing session. Also .captcl session script log file was available as it is written in the manual. Since 1st and till the 7th hotfix neither command window echo nor .captcl session script log fileare available, and this was my ultimate source of examples.

What can be done to get both features back? (Apart from uninstalling all of the hotfixes.)

BTW, I use Win7/64 and tried to run Capture as administrator, if this info may help.

Best Regards,

Azef.

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How to use the Orcad Capture TCL command to find Objects connect by a selecting wire

July 17, 2014, 10:56 pm
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Hi All,

I`m trying to get the objects which are connecting by a wire I select,

so I iterate all thing in a page and try to find if there are matching netname with the selecting wire,but it is Inefficient.

How can I do with another better way?

Thanks!

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How to set the DRC parameters with In AC Manager?

July 18, 2014, 2:47 am
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Hi.. For my design the track to track, track to pad, track to via,via to via, via to pad ,pad to via, route settings to be set is 0.308mm. But how can i set the rules for the spacing constraints in AC manager. How to set the rules before the routing is performed? Thanks & regards Dhamodharan
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Step Package mapping option not finding in setup menu

July 18, 2014, 5:31 am
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Step Package  mapping option not finding in setup menu in allegro 16.6 P004.

Plaese help me how to enable it. 

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Problem with D-latch pspice netlist

July 15, 2014, 12:43 pm
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Hello Experts,

I have a d-latch pspice netlist, when i try to simulate it Iam getting a clipped output that is for the input of 1v I am getting output as only 0.5v . what should I do inorder to get the full output voltage of 1v. q and qb are my output nodes. Please help me.


*d latch
vd d 0 dc 1
ve e 0 dc 1

*inverter
m17 out d vdd vdd pmos l=0.18u w=0.72u
m18 out d 0 0 nmos l=0.18u w=0.36u
vdd vdd 0 dc 1

*and1 gate
m19 nand1 out vdd vdd pmos l=0.18u w=0.72u
m20 nand1 e vdd vdd pmos l=0.18u w=0.72u
m21 c out nand1 0 nmos l=0.18u w=0.36u
m22 c e 0 0 nmos l=0.18u w=0.36u

m23 and1 nand1 vdd vdd pmos l=0.18u w=0.72u
m24 and1 nand1 0 0 nmos l=0.18u w=0.36u

*and2 gate
m25 nand2 e vdd vdd pmos l=0.18u w=0.72u
m26 nand2 d vdd vdd pmos l=0.18u w=0.72u
m27 c1 e nand2 0 nmos l=0.18u w=0.36u
m28 c1 d 0 0 nmos l=0.18u w=0.36u

m29 and2 nand2 vdd vdd pmos l=0.18u w=0.72u
m30 and2 nand2 0 0 nmos l=0.18u w=0.36u

*nor1 gate
m31 c2 and1 vdd vdd pmos l=0.18u w=0.72u
m32 c2 qb q 0 pmos l=0.18u w=0.72u
m33 q and1 0 0 nmos l=0.18u w=0.36u
m34 q qb 0 0 nmos l=0.18u w=0.36u

*nor2 gate
m35 c3 q vdd vdd pmos l=0.18u w=0.72u
m36 c3 and2 qb 0 pmos l=0.18u w=0.72u
m37 qb q 0 0 nmos l=0.18u w=0.36u
m38 qb and2 0 0 nmos l=0.18u w=0.36u

*display
.tran 1n 10n
.probe


.MODEL NMOS NMOS
+ LEVEL = 3
+ VTO = 0.41
+ TOX = 2.2E-09
+ NSUB = 2.0E+18
+ NFS = 6.0E+12
+ XJ = 6E-8
+ LD = 9e-9
+ UO = 390
+ VMAX = 2.2E+05
+ THETA = 0.80
+ ETA = 2.8E-03
+ KAPPA = 0.2
+ GAMMA = 0.40
+ RSH = 500
+ CGSO = 3.33449e-10
+ CGDO = 3.33449e-10
+ CGBO = 0.0
+ CJ = 4.96491e-3
+ CJSW = 2.45744e-10


.MODEL PMOS PMOS
+ LEVEL = 3
+ VTO = -0.41
+ TOX = 2.2E-09
+ NSUB = 2.0E+18
+ NFS = 6.0E+12
+ XJ = 6E-8
+ LD = 9e-9
+ UO = 175
+ VMAX = 1.1E+05
+ THETA = 0.80
+ ETA = 2.8E-03
+ KAPPA = 0.2
+ GAMMA = 0.40
+ RSH = 500
+ CGSO = 3.33449e-10
+ CGDO = 3.33449e-10
+ CGBO = 0.0
+ CJ = 4.96491e-3
+ CJSW = 2.45744e-10
.end
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