Hi all,
I am wondering if its feasible to create a region/area to avoid thru-hole pin in Allegro 16.6 ?
Thanks,
TDP.
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No thru-hole pin region in Cadence
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Importing netlist removes all BGA vias
We're way behind on updates and a recent one was finally installed. Now when I import Logic it removes all the vias under my BGA.
I tried fixing the part and vias but I get this error if I don't check the Ignoge Fixed property. The part nor the schematic symbol hasn't changed from when I initially laid out the board months ago.
So it either tears up all my vias or won't come in.
#1 ERROR(SPMHNI-175): Netrev error detected.
ERROR(SPMHDB-195): Error processing 'U31': Cannot modify element; the object or a parent has the FIXED property. [help].
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Netlist Import "Name Too Long"
Hi Everyone,
So I'm trying to import a netlist to Allegro 16.6 from Capture CIS. When exporting the netlist I set the Device/Net/Pin/Name Char Limit to 255 in Capture. I also have the LONG NAME SIZE in Allegro set to 255.
When I try to import the netlist to Allegro I get the error of Name Too Long for several parts. These parts had imported just fine previously!
I did notice on the bottom of the error log that NET_NAME_LENGTH says 24. What gives?
Any help on fixing this would be greatly appreciated! Is there a setting I'm missing somewhere?
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Incomplete tutorial files for CM with Design Entry HDL Tutorial
Hi,
I was reading "Allegro® Constraint Manager with Design Entry HDL Tutorial" section 2 and doing tutorial excersices. Unfortunately, my files differe from what I see in figures of help and I can't keep on studying tutorial any longer. In section 2 of this tutorial I need to modify Min/Max Propagation Delaysof a net in constraint editor but it doesn't have such constraint. Is there anybody who knows what's wrong with this tutorial? I am wroking with Allegro 16.6.
Help figure:
https://drive.google.com/file/d/0BzS3_lT7y4tEa2x6SER0dFFnWEU/edit?usp=sharing
My file:
https://drive.google.com/file/d/0BzS3_lT7y4tEVWM1SFV4UzRTdFk/edit?usp=sharing
Thanks in advance,
Hossein
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Design Entry CIS Standard BOM Template Title
I have a two part question regarding the CIS Standard BOM report template.
First, is there a way to change the title (header) that prints out on the report? Not only is it not what I want, but it prints way off center so that some of the title actually gets clipped off.
Second, can I save a template that would show up in the drop down list of Standard reports?
Thanks.
Chad
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Schematic Symbol Libraries
Sorry guys, I'm pretty new here. I'm starting a small project, but I couldn't find any schematic symbol that I need, not even a 100 pins connector. I thought OrCAD comes with some libraries, but what I found are very limited. I'm wondering if I installed it correctly or I will have to create every symbol that i need myself? or is there a place I can download them? both schematic symbol and pcb libraries. Thanks for your help and advise.
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allegro 3d viewer
I am a begginer at PCB designer 16.6.
I tried to set a solid view for one of the layers (let's say TOP Layer) at the 3d viewer, but all I see is the FRAME of the layers.
How can I setup this so I can see full plane layer?
Thanks
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A GenCAM from Allegro
Hi cadence
I want to know that is it possible to generate GenCAM file from cadence allegro 15.2?
Please let me know ASAP.
Waiting for reply.........
Originally posted in cdnusers.org bynaren_thesia
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How to create negative artwork or pdf?
Hi!
First, sorry for my bad english.
I'm not an allegro expert, i use it rarely.
I'm using allegro PCB Editor 16.5. So far i used positive artwork files and pdf-s in my designs for positive pfotoresist technology.
Now i have to crate artworks or pdf files for negative photoresist etching.
Of course it is simple if i just convert from positive to negative, but thats a big black film if there is little net.How can i create a negative file if i want to print only the clearance on the copper pour? I don't know if i am understandable or not.
I placed a dynamic shape on my old designs, and on the screen it looks good, but thats still positive. If i change the layer to negative then the clearance disappear between the lines and the shape and everything is merge into the plane.
Is there a solution?
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What the drill size to be use in BB vias?
Hi..
I am trying to work on the six layer PCB board. In that i had configured BB via for the layers what ever to be used in the board. But my doubt is for through hole via i had specified the drill and pad. For the BB via configuration whether we can use the same through hole via size or to provide the new drill and new pad size for the BB via configuration.
BB via definition is pad size should be smaller or larger than through via size. Any idea about the configuration???
Thanks & Regards
Dhamodharan![]()
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Drill hole size minimizing in NCdrill Parameter
For my board file, i had placed the NC drill legend below the board. After that in case i want to minimize or maximize the drill sizes in the drill parameter is not get edited.
In case of layout, the drill sizes can be directly edited in the table.But how it is possible in PCB editor.
For Eg: 0.8, 0.864 drill sizes should be maximized to 1.0 means, how can i edit the drill sizes. any way to change the drill sizes in the parameter table.
Thanks & Regards
Dhamodharan![]()
In case of layout, the drill sizes can be directly edited in the table.But how it is possible in PCB editor.
For Eg: 0.8, 0.864 drill sizes should be maximized to 1.0 means, how can i edit the drill sizes. any way to change the drill sizes in the parameter table.
Thanks & Regards
Dhamodharan
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Is there any community for sigrity?
Hi..
Is there any community for the sigrity SI & PI analysis??????![]()
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how to browse JEDEC type in concept HDL in allegro 16.5
Hi,
Any one can help me for how to browse JEDEC type in concept HDL? and I have alredy assigned library path( pad path and psm path) in PCB editor.I am using allegro 16.5 verton tool
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Orcad Netlist Quick Question
When going through netlisting a design in orcad I get a popup three times that reads:
pstxprt.dat' has changed on disk and has been modified in the editor. Would you like to refresh the editor with the updates from disk, discarding any edits?
I'm not sure what this means and whether to hit yes or no!
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Cadence allegro design workbench installation
Hi all
I'm looking for instruction to setup Cadence adw enviornment (server/client), or recommended setup. I'm not able to find such info any where yet (still looking).
Does any one know a good link?
Thanks
Kevin
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Changing Text Class
After finishing my board design I realize all my Ref Des have changed to the Manufacture class and Autosilk_Top subclass. I want to change them into the Ref Des Class with Silkscreen_Top subclass generally.
in Placment mode I have tried many times by Edit> Change menu with Option Tab but any of them doesn't work
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Constraints for fanout
Hi,
I want to create some rules for Allegro PCB when it creates fanout for my BGA. I have defined two types of VIAs and I want to force Allegro to use one VIA - and thick track width - for Power& GND pads and other VIA - with thinner track width - for signals. Where can I define such rules?
Any suggestions are welcome.
Hossein
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How to add region name property to a coppied shape
Hi,
I have drwan a Rectangle for a constraint region with a region name. Now I use Z-Copy and create another Rectangle for other subclass of my constraint region. The problem is that this coppied shape doesn't have any Region name like the Original one. I want to know how I can create that Region Name property for it? I should add that I tried to
I would appreciate any help regarding this isssue.
Hossein
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Two boards in 3D view and DRC check
Dear All,
I am very new to pcb editor and I designed a number of boards (4 layer) in layout 10.5.
I need to design two PCBs which will be stacked one on top of other using board to board connector.
Space between two board will have Capacitors, EE type inductor and big connector. How can i superimpose one board on the other
and make sure there is no component clashing etc. I have downloaded latest 16.6 lite with step import capability.
Can anybody help please ?
Regards.
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Why can't change NO_RAT Attribute for a scheduled net
Hi,
When I try to make attribute NO_RAT on for a scheduled net in Constraint Manager I receive below message:
Attribute NO_RAT: value could not be applied to Net CCLK in application
I don't see why I can't do that?
Any comments are welcome
Hossein
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