Hello,
I am merging two PCB layout into the same panel. I did merge the schematic first, and then import one PCB layout into another design. This process takes a lot of time and energy.
I am just wondering is there anyother way or software could simply merge two pcb layout together. Not too expensive~~
Thanks
At one time I experimented with BOM Variants. It wasn't what I wanted, so I deleted it. Now every time I open the design, the Variant Name is in my title block and it shows up on the schematic page. If I Delete it, it goes away, but it always comes back. How to I get it to remove permanently? I looked in Part Manager, and there are no BOM Variants anymore. Where does this come from?
Hi,
I am doing IR drop analysis for the 1st time. I am finding difficulty in understanding the Temperature rise results in Options.
Report only mentions the voltage and currents at various points in that power net. It doesn't mention temperature at different points.
1. How to make report to show temperature at all points (as like Current and voltage)
2. Near to the regulator Vout where rail is generated, temperature is showing 167 DegC. Is it Ok or too much. How to decide about safe temperature of these copper planes/traces.
Is it possible to use other 3D formats in the PCB footprint for 3D modelling. There are a large number of 3D models already created using the .stp file extension (3D central for example).
But the 3D output from Allegro is extremely basic at best. I need to view the 3D models better. We also use Altium at this location, it's 3D package modelling is excellent but our head office wants us to standardise to Allegro. This would seem a backward step if we cannot create better 3D models within the Allegro package.
Wondering if there is an easy way to do this?
Say you have an IC with pin numbers 1, 3, 5, 7, 9.
If I use the "auto connect to bus", and when the Enter Net Names window pops up, I enter:
U1.[1..9].
It will give net names that increment like this (which makes sense since there are only 5 nets)
U1.1, U1.2, U1.3, U1.4, U1.5
Is there a way to change it so that it increments 2 at a time, instead of 1?
Thanks!
Hi All,
I was wondering if there is a skill script that will allow me to re-size the text of a symbol.
Each time I have to do this, I need to go to setup->Design parameter-> text tab and select setup text sizes and then have to insert the
desired width , height etc to make it look nice and readable.
If there is a skill function of for this that would be great.
Many Thanks,
Nik
I am having a problem trying to rout some differential pairs in Allegro PCB Designer 16.5. When I try to add a connect line to an existing differential pair, it only allows me to draw a single trace, and the single trace mode option in the right click menu is greyed out. This is only happening on certain differential pairs and not others. I have no idea what's going on and could use some help!
Thanks!
-Daron
Hello, i am facing problem without fan out feature of auto router with pcb editor.Images of before fanout and after fanout are attached. please advise.
Adeel
Hi,
how to merge two pcb's in allegro??
Regards,
Amal
I'm using Cadence OrCAD 16.6 Lite version. I'm able to design a circuit using MOSFETs and simulate it.
Does this version provides the advance functions such as layout designing, PCB routing, etc. ?
How should I specify the Technology File?
Hello,
I have a question about BB VIA. I have a 6 layers board, which needs BB VIA.
If I connect from top layer to third layer, should I use a layer 1 to layer 2 bb via then layer 2 to layer 3 bb Via, or I need define a bb via from layer 1 to layer 3?
Thanks
When using Allegro PCB, how can I specify the path for the generated artwork? Currently it just dumps the artwork files in the Design directory, whereas I would like the artwork to go to a sub folder
.../design_directory/artwork/
Hello,
I am merging two PCB layout into the same panel. I did merge the schematic first, and then import one PCB layout into another design. This process takes a lot of time and energy.
I am just wondering is there anyother way or software could simply merge two pcb layout together. Not too expensive~~
Thanks
Hi
I have to layout a hairpin filter at XBand in Oracad layout V10. I have a dxf of the filter and it is only on the top layer. It does not use padstacks and it has a rather complex geometry - gaps, turns, and transmission lines. How do I place it on the layout of the artwork as a component? Preferably I would like to use the dxf.
Thanks for any help.
Hello,
I create hierarchical blocks to implement a piece of schematics that should be impemented severla times. When running the Design Rules Check (DCR), I am getting the warning "WARNING(ORCAP-1629): Multiple Hierarchical Ports of same name exist across Hierarchical Blocks". I would like to know what does it implies and how to fix it.
Best regards,
Ezequiel
For adding jumpers to PCB Editor need to edit drawing property "Jumper list"
I added in box one name, for example "jumper" and all work.
I tried adding two or more jumpers and faced with the problem - separators ",", ";" don't work for this property. For example, parameters
jumper, jumper2
jumper; jumper2
jumper jumper2
perceived as a single item of list.
How I can added two or more jumpers? Which separator I should use?
I need to display the voltage through a 3 Ohm resistor. I was able to simulate it, but I can only figure out how to get it to display the node voltages.
Thank you.
Hi,
Mostly i will update my design Intersheet Refernce(IREF) with the position "Offset Relative to port" in order to get the Intersheet refernce aligned properly with respect to off page connector.
In 16.5 cadence tool,its perfect and working fine.
In 16.6 Cadence tool,i facing an issue with the intersheet reference adding with the 'Offset Relative to port" option.
The issue is that instead of aligning on the left side of the off-page connector/port,it is placed on the right side and vice versa.
Please see the attached picture for more details..
The same schematic design,the IREF is plaed correctly in the 16.5 version,i am facing issue with only 16.6 version.
Are anybody face this issue with 16.6?
If you have solution,please let me know.
Thanks in advance for your help..
Regards,
Vel