Hi,
I run into this DRC error and wonder if anyone has experienced the same and know how to correct it. I am using OrCAD PCB Designer Standard and OrCAD Capture 17.2 for this project (and I am new to this PCB Designer).
This section of the board consists of 6 relays (Panasonic JS1-5V-F) driven by two ULN2003 SOIC-16 chips. For clarity, the net names are as follows:
- Control signals from CPU to ULN2003 inputs: OUTPUT[1..6] with OUTPUT[1,2] go to one ULN2003 and the rest to the second ULN2003 (and their outputs drive the relay coils)... trace thickness 10mils
- Relay contacts: OUTPUT_C[1..6], OUTPUT_NC[1..6], and OUTPUT_NO[1..6] (these three pins connect directly to the 3-pin terminal blocks)... trace thickness 150mils
In the constraint manager, I initially assigned a 50 mil clearance for all these OUTPUT nets across various columns (Line to >>, SMD Pin to >>, etc...) using Spacing CSet. When I started routing the OUTPUT[1..6] nets, various DRC errors popped up at the ULN2003 chips. I realized my mistake by having 50mils clearance for all OUTPUT[1..6] nets. I then removed these nets from the class and used default values of 10mils clearance for all instead.
This cleared a few errors, however, the SMD Pin to SMD Pin DRC errors remain with P><P indicators in between ULN2003 pads as well as capacitor and resistors pads on the associated nets. I deleted partial traces to the chips and rerouted these nets. This cleared the errors on the first ULN2003 chip with OUTPUT[1,2]. Strangely, these errors remain for the OUTPUT[3..6] nets on the second ULN2003.
When I opened the constraint manager to look for more details, the DRC Spacing window says 10 mils for Required and 18.5 mils for Actual (which is correct for the ULN2003 footprint I use - 1.27mm pitch and 0.8mm pad width). This should not generate any errors. It seems the software does not use the updated 10mils clearance for errors checking even it logs the value correctly. Closing and opening the software does not make any difference. The change that I made maybe corrupts the design database somehow?. I am a bit lost at this time. I just wonder if anyone has any idea how to resolve this.
I have one more question unrelated to this error. Currently I have a 150 mil trace for each of the OUTPUT_C/_NC/_NO[1..6] nets on the top layer. I would like to have 300mil in total for each trace (for higher current) by adding another 150mil trace on the bottom layer. How do I do that?. I have tried using Shape/Polygon connecting the two pins and assigned the same net name. It seems to work but when I draw the polygon near the pin center, the software adds something like a + sign at the pin with 150 mil thick, which is very messy. I tried to Add/Line etch with 150mils but cannot assign net to it. Line is much cleaner and easier to trace over the existing routes.
Any hint/help would be very much appreciated. Thanks.
TC