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Error: Table name not found in dbc (CIP)
Hi The above error is still showing up even when i have setup dbc file again.Also, some of the parts in Part Manager window do not have any part number assigned to them.
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Custom reports - how do I get a list of net pins
I am trying to generate a custom report similar to the Net List report.Where do I find the actual file used for the report ?Or how do I get a list of a net pins in a custom report ?
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Place Arduino Uno or ATmega328 part in Capture
Hi. I'm new to the forum, so I'm not sure if I'm posting in the correct place. I'm trying to figure out where to find an Arduino Uno or ATmega328P to place in my schematic. Is this possible, and if so,...
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How to take over a design from an outsource
My company outsourced a design of a complex board and now we would like to take over the design for ourselves. Problem is the contractor database part numbers don't match up with our part numbers even...
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DRC error: route keepout spacing
helloi have a route keepout spacing error.i do know that i can allow "vias", "routes" (clines), "pins" and "shapes" in the keepout shape area by changing the shape properties.but i get this "line to...
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Write protect a Cadence Capture project
Hi,Is there a good way to write protect projects in Cadence Capture? I like to have multiple previous projects open to copy paste from etc. but always worried will save some unintentional changes.Maybe...
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find filter control
hellois there any way to control what items to display on the find filter?currently as default, there are so many items on the design object find filter that are not in use so i want to remove the...
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Footprint
Hi,How to draw a gold finger connector in orcad 17.2??Kindly guide me.Thanks in advance
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VIA selection for Automatic Router
Hi,I am using the Autorouter and by setting the constraint of Min Line Width inside CM I can control the width of the trace for a specific Net, but how can I control what VIA a specific Net shall use?...
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Replace Blind Via with Blind/Buried Stacked Via?
Hey guys,I have a 10 layer design with a Blind 22/8 via from layers 1-9. I need to have a blind micro via from L1-L2 on the top of this via. Is there a way to do a global replace of my L1-L9 via with...
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OrCAD Capture 17.2 Start Screen
I'm looking for the way to disable the OrCAD schematic start screen. In version 16.5 there used to be a way to do it by editing some extended preferences. However that part of the menu system changed...
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OrCAD User Assigned Reference Unset
In the last few years OrCAD schematic added a feature where when a user edits the reference designator of a part it underlines it to show its been edited. I really wish it would not do this. To make...
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DRC Error - SMD Pin to SMD Pin
Hi,I run into this DRC error and wonder if anyone has experienced the same and know how to correct it. I am using OrCAD PCB Designer Standard and OrCAD Capture 17.2 for this project (and I am new to...
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Frustration in getting bugs fixed
Hi all,I have submitted a number of CCR's with what I find are bugs in the software only to have the CCR placed in the inactive pile. For me this means it will probably never get fixed. Others are left...
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After updating the OrCAD CIP Server to v17.2.13.4 the server no longer starts.
My channel partner, EMA Design Automation, recommended I update my CIP Server and Client to the latest version. After the update, CIP Server won't start.This is the information the CIP tab displays in...
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Creating Netlist Error
I am trying to create a new netlist from a file that I modified in OrCAD capture. When I run tools > create netlist the following error occurs: Error: Schematic supports creating XNets for passive...
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Changing Line Width of a Trace in a Net without DRC Errors
Hi,I would like to know a way to change the line width of a trace within a larger net without DRC errors.I have a net with 100mil line width assigned to it. There are several traces branching off from...
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Netlist generation _Ocard -Allegro with diferent reference designator)
One our Costumer has the ownership of SCH, but in the latest SCH update that he sent, he changed all the ref-des (all the placemen in the layout was a swapped or changed).There is any way to load the...
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Update net names and net groups in an existing design
Hi Cadence,I need to rename some nets in my design and they are part of netgroups I created previously. However it seems renaming netgroup instance name is not that easy, since there is no rename...
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Regarding making of library in allegro_design_entry_HDL?
In allegro_design_entry_HDL as libraries i am getting and that i have created using Padstack editor is of format .jrl, .psm, .tag, .log, .dra, .psm, .dra.lck. But in Allegro_design_entry_HDL the...
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