Quantcast
Channel: Cadence PCB Design Forum
Browsing all 5525 articles
Browse latest View live

Image may be NSFW.
Clik here to view.

Connections on pads between overlapped components

Hi every oneI have design with 2  BOM warians where two symbols from  different BOM variants overlapped each other :this is  4-port rj45 connector and 1-port rj45 connectorThe problem is that I can not...

View Article


Image may be NSFW.
Clik here to view.

Need to create Open mask pad

HiI need to create a open mask pad, i need only bare copper to solder the pad with external wireIf i i make Soldermask TOP as NULL,  it is OKPlease answer my query

View Article


Image may be NSFW.
Clik here to view.

Can Constraint Manager run Analysis when open ?

Is there any way to have constraint manager run analysis on all nets and all columns when you open a screen automatically?

View Article

Image may be NSFW.
Clik here to view.

SPB 17.2 problem

Hi,I've just Installed 17.2 but behaves a little bit strange.A new Analog or Mixed A/D project opens with all the simulation buttons enabled even if no profile was previously created.The same is true...

View Article

Image may be NSFW.
Clik here to view.

Why Hierarchical Variant disabled in Allegro Design Entry HDL 16.6-2015

The User guide PDF suggests three reasons, but doesn't explicitly say how to solve it:1) "There is no variant information in the lower-level block (reusable block).">I have created variant data for...

View Article


Image may be NSFW.
Clik here to view.

Matched Lengths using constraint manager

Has anyone used constraint manager to do matched lengths. I find that there are lots of bugs in using constraint manager and relative prop delay. Just curious if anyone else does this and how dos it...

View Article

Image may be NSFW.
Clik here to view.

net list importing problem

Hi all,in cadence 17.0while  creating the net list in Orcad capture under path  input board file and  click on ok,it is showing on error flows. find below snapshot.in board file there no errors.please...

View Article

Image may be NSFW.
Clik here to view.

down conversion problem in cadence 17.0

how to down conversion from cadence 17.0 to cadence 16.6 i have try but i get error massage "down rev of 17.0 databases to 16.6 is not supported please help me any one 

View Article


Image may be NSFW.
Clik here to view.

Allegro PCB editor Step files not visible?

Hi..I had installed the orcad 16.6 with the hotfix of 046 update. So i am able to work on that clearly. But while i am mapping the components on Step mapping option, the corresponding step symbols in...

View Article


Image may be NSFW.
Clik here to view.

Microvia hole to line clearance. No DRC error ?

I am using micro vias and set the line to hole clearance at 8 mils. It is enabled in constraints  and should produce a drc error. Even if I place the trace through the microvia hole I do not get a DRC...

View Article

Image may be NSFW.
Clik here to view.

pspice smoke analysis

hi have built a citcuit in pspice a regulator circuit with pass transistors for more current i am using igbts but when i run a smoke analysis its tells me the max power dissipation is is to high for...

View Article

Image may be NSFW.
Clik here to view.

How to update parts already placed from the Database

Hello,I've been using Design Entry Cis 16.6 and I have an already finished big schematic with all components added from a Part Database (which is configured on the company's network).All the components...

View Article

Image may be NSFW.
Clik here to view.

padstack

I created an irregular padstack and the routing trace connected to the center of the pad where it has no copper (irregular shape). How can I move the connecting point to somewhere it has copper on it?

View Article


Image may be NSFW.
Clik here to view.

Allegro PCB editor; Auto rename refdes issue.

HI,My issue is that when I run a Automatic rename refdes, a few parts are left out from being updated.These parts keep their refdes, the other parts are updated, no duplicate of refdes.I have checked...

View Article

Image may be NSFW.
Clik here to view.

Ref Des control with Heterogeneous parts spanning multiple pages

I've implemented ref des control on my schematic and have a heterogeneous part that spans multiple pages.  This part is U1 in my schematic.  U1-1 appears on page 1 and U1-2 appears on page 2.  Page 1...

View Article


Image may be NSFW.
Clik here to view.

Board Geometry OUTLINE subclass warning

Hi,I have always used the Board Geometry OUTLINE subclass for my board outlines.  My board house wants a 1 mil trace on one of the layers as the board outline, so I've been using that subclass and...

View Article

Image may be NSFW.
Clik here to view.

Problem with rotating component using iangle

Hi,At the moment I'm using Allegro 17.2. For rotating components I use the iangle function: funckey r iangle 90Normally it rotates the component perfectly in placementedit mode, but for some designs it...

View Article


Image may be NSFW.
Clik here to view.

How to set zoom button factor settings in pcb editor?

Hi..,       I am using the Allegro PCB editor 16.6, In that while i try to zoom the specifie component means i want to scroll three to four times.For our indian standard, currently we are using mm...

View Article

Image may be NSFW.
Clik here to view.

PADS import Error

Hi,I have found some PCB symbols for a component - LTM8001 - which are in PADS format. I was going to use Allegro-> import-> CAD Translators-> pads to convert this symbol to allegro format....

View Article

Image may be NSFW.
Clik here to view.

turn off alt symbols not found during import netlist

Is there a way to to turn off reporting of warnings for symbol not found for alternate symbols?

View Article
Browsing all 5525 articles
Browse latest View live


<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>