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PADS Translator of PCB and Library loose all the swappability info
I have done some test and seems that Pad Translator loose any swappability info of the components.It generate always 1 gate containing all the pins.Also all the pins are NOT swappable.the same appens...
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Page Order in Hierarchical Design DE-CIS 17.2
Is there an automated method (not manual) for controlling the page ordering in a schematic design with a complex hierarchy? Manual editing will only cause problems as pages are added and deleted. For...
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How Allegro is calculating Via delay (Z-axis delay) from propagation velocity...
Hello Group,I really had a hard time to identify formula through which Allegro is calculating via delay (z-axis delay) from propagation velocity factor.In CM, default value for propagation velocity...
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Possibility to open Cases and how to ask improvements on PCB designer
Hi, i need to know how to open Cases (because when i login inside the Support i dont have the button to open new cases,but strangely i can see the possibility to see my cases already...
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Possibility to open Cases and how to ask improvements on PCB designer
Hi, i need to know how to open Cases (because when i login inside the Support i dont have the button to open new cases,but strangely i can see the possibility to see my cases already...
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File Type Clarity - Using Built-in Capture Symbol Models to Create...
What I'm trying to do... I need to simulate two NMOS transistors each with custom parameters. I would like to have my own Library in which I can build individual non-associated (meaning: if I...
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PQ and EFD 'family name' in MAGNETIC PART EDITOR
Hello,To Create PQ and EFD family type transformer in magnetic part editor?Is there any way in data entry to provide PQ and EFD Family As well?regards,jishu
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Recommended method of defining generic microvia padstack
What is the recommended method of defining generic microvia padstack in PCB Editor 17.2?My attempt was making a regular via padstack with all layers defined. Then go to Setup > BB via Definitions...
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Dynamic Shape loses connectivity after stretch
Dear All,I have a shape made of dynamic copper on TOP. There is a net assigned to it (RL), as you can seeWhen I stretch it it loses the connectivity, becomes unfilledand gives error in status: Dynamic...
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BGA Generating Footprint With both blind and thru fanout
Ok, I'm stuck......I have a 144 pin 0.5 pitch BGA that I want to make a footprint which includes the fanout. Signals will use a blind via from the top layer to the second inner layer. Power pins will...
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Orcad CIS database Microsoft Access Error.
I am able to open CIS explorer to see folders which were pulled from from My Access Database but I have the following errors that appear:ODBC Error Description:...
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CIS database -> Error(ORCIS-6245): Database Operation Failed
Hi, I am having some trouble with my CIS database in Orcad. After opening the CIS Explorer and then click on a part I get the error below. After clicking OK in the dialog box I am able to place the...
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How to turn via merging off
Hi,Is it possible to turn off via mering?For example I have a 12 layer board. If I place a via from 5:7 and place one from 7:9 on it, it merges them together to 5:9. I don't want them to merge, so I...
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component index in netlist
Hi allI'm trying to understand the netlist file generated by Orcad capture. see screenshotwhat does "I505679590" define and how can i find it of other components?many thanks
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Advantages of High Speed Option?
We are attempting to justify buying the High Speed Option for Allegro 17.2. I can find the lists of improved functionality, but I need to write up a presentation that states in layman's terms what we...
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Trace Length Matching
Is there an "automated" way to match trace lengths (defined in a match group) other then setting the longest trace as the "target" and then using the manual slide tune tool to bring all of the traces...
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Differential Pair Via Spacing
When routing a differential pair and transitioning to another layer, the via spacing is wider then I would expect. For example, I have the diff pair trace to trace spacing set for 0.3mm but the vias...
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Extract netlist on specific area
Hi,I'd like to extract all the nets that is routed in a specific are on PCB on each layer. For example I have a component U10, and I'd like to see all the nets routed around it that is max 5mm away.Is...
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Allegro PCB Designer - removing the circuitry outside of an area
Hi,Is there any easy way to define an area of pcb, then removing anything else outside of that area? But the routed signals, components etc won't change inside of the area?
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To get resistance of track
Hi all, I'm looking for a easy way to calculate tracks resistance about my board. I have compiled the cross section with thickness. Is possible get the resistance in DC/frequency about specific tracks?...
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