16.5 Flow Manager / Packing and Check Model Issue.
I am migrating from 16.2 to 16.5. My company maintains a released library for schematic capture (schematic parts, allegro symbols, costing etc., dml models) This is a pain since it may take upto a...
View Articleimport .STEP file in PCB editor 16.5?
hi,How to import .step file ( Connector Component ) in allegro PCB editor 16.5.Thank you,Raam
View ArticleHow to learn Hierarchical design ??
Hi every one ,in my design Powersupply,Buffer,FPGA section and Reset circuit is there i need to do in Hierachical design i don't know how to start the hierarchical design .what is the use of...
View ArticleOutput "active net" to the CIW or Skill Development window.
Ideally I would like to add something to my funckey line to output the active net to either window. funckey a add connect Thanks in advance for giving me input.
View ArticleDisplaying single ratsnest
How do I turn off or on specific rats (16.6)? Say I only wanted to see the +12v ratsnest, or I wanted to turn off the GND rats nest. Along those lines (no pun intended...) PCB Editor gives you the...
View ArticleCopying vias
I recently did a job where I had an area of copper and used the copy command to copy a via to create a small area with multiple vias to the plane below. Very neat and useful feature. A lot easier then...
View ArticleAllegro Hangs with new hardware
We recently got new hardware and Allegro (16.3) will hang on occasion with the hew nardware. Has anybody else experienced this.New Hardware is Dell Precision T5500 running XP with Nvidia Quadro 2000...
View ArticleDesign Entry HDL - Hotkey saved file
Is there a file somewhere that stores the user customized hotkeys (under tools, costomize, keys)? I would like to share my custom hokeys with other users. Thanks.
View ArticleDesign Entry HDL - Multiple Commands per Hotkey
I am trying to create a hotkey that will perform multiple commands at once--for example, set the grid size to 0.05 and then refresh the screen. Or for example perform the operation of Group->Text...
View ArticlePreferred Method to Indicate Non-Populated Components
What is the preferred method for indicating components that aren't populated in OrCAD Capture 16.6? Do I just simply add text next to the schematic symbol that says "Do Not Populate", or is there...
View ArticleHlp with pcb design
Hello,I am a student and i am having problems with understanding a certain pcb design. You can find the pcb here: http://pdf1.alldatasheet.com/datasheet-pdf/view/449682/TI1/LMR62014.htmlWhat i don't...
View ArticleNetlist import removes placed components
I have a schematic that has had several parts changed on it. The footprints remain the same, but either the symbol has changed or a part value has changed. Whenever I import the new "logic" the many of...
View ArticleAutorouting
I normally don't autoroute anything, but I'd like to try it on a board I'm working on. Problem is this board is 8 layers and my seat is limited to 6 layers. I'm thinking I can remove the layers where I...
View Articleproblem in Annotation ??
Hi everyone,in my design i cut the schematic symbol from one page to another page the part reference is changing what is problem ??from my schematic design i come to know in annotation mode is changed...
View Articlecomparing schematic netlists
Good day all, I have a thru-hole board in Orcad Layout. I have completed a smt conversion of the board in Orcad PCB Editor. While updating the schematic I spread it across multiple sheets since we...
View ArticleHow to Create Custom holes in PCB Board design
Hi, I have been developing a simple PCB board which contains a PIR sensor, an LDR and some other discrete components along with MSP430G2231. I have done outlines for my board according to its...
View ArticleDesign Entry HDL - Console command to move to next page
Is there a console/script command to move to the next page? I would like to be able to perform operations on the entire design as opposed to just one page at a time. Thanks.
View ArticleMultiple SRAMs 1 data bus
I am creating a pcb with multiple srams connected to an FPGA on 1 data bus. I intend to clock the srams and the fpga at 150 MHz. I am concerned about what issues will arise when connecting mutliple...
View ArticleLaunching CIS taking up a Layout Seat
I am unable to launch CIS independently. By opening CIS I am taking up a layout seat too. Any ideas as to what is going on?
View ArticleAllegro DFA
Hello all,I would like to hear about users that are successfully using allegro DFA and have integrated their contract manufactures rule set into this process and how the integration was accomplished....
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