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PSpice Model Editor v16.5: What versions of IBIS are supported?

The PSpice Model Editor IBIS Translator option fails to translate a Fairchild NC7WZ02 IBIS file.  I've included the first 21 lines below.The translator stops at line 10 with "ERROR (line 10) - Invalid...

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IBIS model simulation

I am designing a Data acquisition system with a Texas instruments ADC, Inamps and a ST micro electronics micro controller. I am getting spice models for my inamps, differential amplifiers etc. so that...

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Concept HDL Net list Importing error in VLCT RASP HIP cadence 16.6 PCB

Hi,      I have following error while importing netlist in VLCT RASP HIB SEED PCB. Anyone can help me to clear this error. #1 WARNING(SPMHNI-192): Device/Symbol check warning detected....

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Regarding Artwork option ??

Hi eveyone,i have some doubt for Leading and Trailing Zeros.instead of leading Zero if i choose trailing zero what will happen.what is the use of Gerber RS274x why should i choose that format .if i...

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ODB++

We are having problems with the ODB++ information not matching the placement information or the IPC-2581 output. We have some parts placed on the board at strange angles and the output from ODB++ is...

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Artwork form Control problem with film options

 Hi all,While I was finishing a pcb design I get into this issue trying to get the gerber files. The problem is that I am missing the "film options" tab on the Artwork form control, I tried to...

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cadence version 16.6. anyone having problems with this version

About to install v16.6, does anyone have any problems with the new version that I need to know? Appreciate any feedback.

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Files missing in packaged directory,

 After creating a netlist of the desing. Upon importing the netlist, the error message below occurs. It is asking for pstcmdb.dat and pstcmbc.dat. Neither of these filesa rein the Packaged directory. I...

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Copying components from design cache to library removes user defined properties

Hi, I'm running OrCAD Capture (no CIS) version 16.6 and having some trouble.Here's my scenario ... I create 3 resistor symbols in a library named "R 10R", "R 100R" and "R 1k". After placing these 3...

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show grid settings

Is there a way to see current grid settings on the screen, or do I need to go to "settings/define grid" just to see current?

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Conflicting values netlist error

Hi all,I got below netlist error after swap pins enable for part(Heterogeneous).. please help me.. #105 ERROR(ORCAP-36004): Conflicting values of part name found on different sections of...

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How to define a Plane Layer

In Orcad PCB Designer, there seem to be two different ways to define a plane layer. Setup > Outlines > Plane Outline and attach a Net and draw a shape.Shape > Rectangle (any shape) > Assign...

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Multi-site design HDL reference designators

 Hi there,HDL DE newbie here.We're doing a multi-site design schematic entry with part name ref des as, say, 1R1; where 1=site num and R1= is resistor 1. I would like to know how to copy the component...

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what kind of VIAs does people use?

Hi,I am new about PCB design. I personaly would like define all kind of via, all kind of combination(as you see in picture 1) I also saw a tutorial shows that only define b/b via between each layer.(as...

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A problem with DC-blocked filter

Hello.I performed a simulation of filters, When I simulated a lo-pass filter, the results was correct. But, when I tried to simulate a band-pass filter, with a blocking capacitor in front- the results...

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Custom Vias

Greetings,I've been on this forum under various names depending upon employment status and I need the forum's help once again. I have a package called PowerBlades. The end mounting to the PCB have two...

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Free Physical Viewer 16.2 - Find Comp functionality

I recently upgraded my free physical viewer from 16.0 to 16.2, and have found that when I use the 'Find By Name' functionality, a successful hit on a component no longer causes the viewer to zoom in...

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PAD_DEF output in 16.6 ISR22

I have just installed IRS 22 for 16.6 and now have problems with the Valor ODB++ output, there is a new field in the standard output which seems to stop this working. PAD_STACK_CATEGORY. Does anybody...

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HOW TO CHECK SEED SCHEMATICS IN CONCEPT HDL?

 pcb tool : cadence allegro        schematic tooi : concept HDL Hi,    Am using seed schematics for tester layouts. usually am editing that schematic and adding circuits.    Here my question is after...

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bom_capture_16.6

i am sure most of you have encountered this. Is it possilbe to increase the string length of BOM generated i.e. more than 255. currently thelimit is 255.currently running without CIS option lic.

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