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How to use the some set of vias under the top to bottom layers?
Hi.. For the specific board design the top and bottom layers should been get connected set of arrays.For that option i had tried to use the thieving parameters. In that rectangle type shape has enabled...
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OrCAD16.6 DRC Error: ERROR(ORCAP-2207): Check Bus width mismatch
Hi,When I run DRC. I receive below message at the end of report file, although I checked the whole design completely:Checking Misleading Tap connectionERROR(ORCAP-2207): Check Bus width...
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Allegro Design Entry CIS - "Select entire net does not work on separate pages"
Hi all,I don't know what happened or i did somethings wrong on my schematic.I previously could select a net that was connected by off-page in 2 pages in 1 schematic by "select entire net" then the net...
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Routing on top and bottom side is possible with any option on etch???
Hi..I had worked on the pcb with two layer board. In old days worked with the layout i use to route the enabled ratsnest on top side, at connection tool----> make and connection between source...
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DRC & Create Netlist Error(ORCAP-36041): Duplicate Pin Name. Please renumber...
Hi,I have created many parts in OrCAD which have 'NC' pins - or other pins with similar names: IO,.. - when I run DRC or create netlist I see below error messages in the DRC report file or session...
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OrCAD16.6 DRC check problem: "Net has two or more aliases"
Hi, I have used net names of my power symbols for various pins. Running DRC I see below messages. How can I get rid of such messaes?INFO(ORCAP-2212): Check Power Ground MismatchQUESTION(ORCAP-1589):...
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Assign Pattern option ( disable or a way to set it )
I am using the funckey "code below" and now with v16.5 a "Assign Pattern" window is popping up. I am trying to either set the pattern or disable it completely so my "F" key is more effective. Thanks...
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Does IBIS to Pspice Converter Work in ORCAD Lite 16.6.S022?
Hello, I tried converting an IBIS Ver3.2 model from Texas Instruments using ORCAD LITE 16.6; and I get the following error message in my ibis2spice.log file: ERROR: in launching Ibis2signoise. Any...
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Library Conversion form layout to editor is possible?
Hi.. I had maintained some of the power modules in layout 9.2 version. But when i am try to use it for the editor is possible. Any import option is possible from .llb to .dra conversion. No i am using...
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Global Schematic Page Properties, Page Size change for Existing Design in...
Hi,I've Schematic design with more than 100 pages, how to increase the page size globally for all pages instead of doing it sheet by sheet.Please help to update. EDA Tool using: "Allegro Design Entry...
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How to use the thieving parameter in pcb?
I had worked on the pcb, but when i am try to put the set of free vias, i had used the parameter of theiving. When i am try to use it, that has been get enabled for single layer.How to use the...
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Footprint not showed
Hello. I'm using orcad 10.3. I made a footprint, but when it is placed in my PCB design it is invisible. There is nothing in the silk screen layer for this footprint. I can see the drill symbols and...
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funckey
I want to use the keypad home/left arrow etc with funckey. Is there a list of what these keys are called?
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Footprint viewer in Capture schematic
HiI just got a new computer and a new install for 16.6 software program.Having trouble setting up the above to view footprints in schematic capture.In PCB EDITOR user preferences I have set the paths...
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Is Bold Text Possible?
I know how to change my text, Edit > Change, and then use the options menu on the left. But, I don't know how to change the style of the text. I don't mind the font necessarily, but I want large,...
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Orcad Capture TCL scripting
Hi All,I would like to use Orcad Capture TCL scripting. Before the 1st hotfix of 16.3 the command window in Capture echoed all of the operations performed during the editing session. Also .captcl...
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How to use the Orcad Capture TCL command to find Objects connect by a...
Hi All,I`m trying to get the objects which are connecting by a wire I select,so I iterate all thing in a page and try to find if there are matching netname with the selecting wire,but it is...
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How to set the DRC parameters with In AC Manager?
Hi.. For my design the track to track, track to pad, track to via,via to via, via to pad ,pad to via, route settings to be set is 0.308mm. But how can i set the rules for the spacing constraints in AC...
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Step Package mapping option not finding in setup menu
Step Package mapping option not finding in setup menu in allegro 16.6 P004.Plaese help me how to enable it.
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Problem with D-latch pspice netlist
Hello Experts,I have a d-latch pspice netlist, when i try to simulate it Iam getting a clipped output that is for the input of 1v I am getting output as only 0.5v . what should I do inorder to get the...
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