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Can't place via next to pin
Hi,When I want to route some tracks of pins I can't place via just near the pin, while for neighbour pins I can do it easily. I have also defined a Power class net for both of them with pin to thru via...
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paste size vs pad size
When using a rectangular pad, it's easy to make a paste layer a little smaller. First, is this really needeed?My bigger question:When I use acomplex shape to be the pad, do you guys just make the paste...
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Shape filled and unfilled
I'm a new Allegro 16.3 PCB Editor User.. please somebody help me with the following question1) what is in general the difference of using shape instead of lines or rectangle 2) rectangle ( filled or...
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For place bound top and bottom of components solid fill ?
Hi.When i am trying to place the components in the design, place bound top & bottom the outline is get filled with solid.Whether we have to use the solid fill or any other option.Thanks &...
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Slotted Through Hole for mounting appears filled instead of drilled
Hello. I am tryign to make a mechanical non-plated slotted through hole which will allow a device some 'wiggle room' while mounting it on a board. I can't seem to make the slotted through hole appear...
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How to hide the Pin name of the components in Allegro PCB editor
Hi, I am using cadence 16.6 for my layout. When I am placing the components on the board, the pin numbers are visible and it is annoying me. Please inform me how I can make the pin numbers invisible on...
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Problem in Bundle Create
Hi,I have some questions regarding Bundle Create:1- Can I bundle any nets or I must first define Bus in my Schematic? I have connected many Nets using off-page connector and it seems that I can't...
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Upgrade a layout design having modified a component's footprint
How can I upgrade a layout without moving or place again the components when I need to modify the footprint of a component ?I tried to do that modifying the library, and "exporting physical" again the...
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How to match length of a differential Pair
Hi,I want to match the total length of my Diff pairs - all should be in a specified range in comparison to each other. I have defined an Electrical rule set and assigned some min/max margins. Then I...
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Library part management
Hi everyone....brand new to 16.6 Pro...no CIS. I've managed to get far enough on my own with it to send some test gerbers (a few issues came up that I'll post later on) to the pcb house and they said...
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For assemby outlines how to draw it seperately?
Hi.. I had finished my four layer board with allegro PCB editor. In that i had drawn the board outline with the outline option. In case, i want to draw outlines for bottom, signal, ground, top layers...
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Network file issues, cannot create .psm or .art files on network. Orcad PCB...
Background:A little over a year ago, engineering was forced to upgrade to Windows7, forcing a re install of 16.5 or upgrade to 16.6. Both paths were chosen, along with a hold out on XP running 16.5,...
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How to view the specific area in the allegro 3D viewer?
Hi. My question is been very silly, but now I'm in beginning stage of the using Allegro PCB Editor. For the four layer finished PCB, i want to view the particular area in the Allegro 3D view with...
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How to import the dxf to PCB Editor?
Hi.. I had imported the DXF from the another system. Some error is been get occured. can anyone specify me detailed solution with step by step procedure for this problem. It's urgent.
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Could I set the layout constraints in Orcad Capture 16.6?
Does somebody know if we could set the layout constraints in Orcad Capture 16.6, for example trace wide, spacing, equal length?And could you please show me the exact command? Thanks!!! Best regards,Frank
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Allegro Design Entry CIS, "Place Wire" question
Hi,This has bit me in the b*tt twice already, and I'm not really sure how to "correct" this issue. In PADS when I started a wire I I couldn't just end it, it had to go somewhere. I'm using Cadence...
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Allegro Impedance Calculator problem
Hi,I am working on my board Stack-up to tune Single/Differential impedances of my board in Allegro PCB 16.6. I see that Dielectric Constant is 4.5 (FR-4) ! even for Conductor/Plane layers. I don't see...
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Ref des text size makes too bigger and thickness in plotting?
Hi.. For the Ref des text sizes in the corresponding layout has been get changed to some size to previewed. Then after ti took to print the SST layer in the A size sheet, that time plot preview of the...
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How to measure routed Clines of a net
Hi,I have some termination resistors on some nets - Address nets of DDR memory - I want to measure total Cline between FPGA ball and DDR ball. If I use Display->Element (F4) with Clines in Find...
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Can FPGA system planner export schematic file directly?
I am a newbie to FPGA system planner, I want to know can FPGA system planner export schematic file (OrCAD DSN) directly?Thanks!
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