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Single layer capacitors and die cavities
I am working on a design with single layer capacitors, bare die and cavities for the die. In the past we handled the die and cavity as an regular component. This is pretty simple and works well. The...
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Find Zero line widths in Allegro design
Anyone have a SKILL script, or another way, to locate all th zero line widths in a design? Chad
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Single schematic for two PCBs?
Greetings, Using Capture 16.0, is it possible to create a schematic for two interconnected boards, and netlist them separately for Layout? The schematic is presently hierarchical, if it matters. Thanks!
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User preference editor was not found in CADENCE?
Suddenly the user preference editor option at setup parameter option is been not opened . The message is "No preferences files found." Any help please.. It urgent.
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DRC error
Hello,I run DRC check on 1 of my design and getting an error"ERROR: [DRC0004] Possible pin type conflict U4,VCC Power Connected to OutputSCHEMATIC1, P02 BUFFER CONTROLLER (11.80, 2.20)"And here how...
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How to set the DRC parametres in Constraint Manager?
I had set the spacing width and all other parameters with the data as provided. Then in layout, Pin to pin spacing, Pin to through hole component spacing,track to tracking,track to via, via to track,...
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How to learn PCB layout?
Good Morning All,I'm currently work as OrCAD Schematic Capture and build Schematic Symbol at work. I don't know anything about the OrCAD/Allegro PCB layout and would like to learn how to do it. I have...
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Cline to Anti-Pad distance DRC
Hi experts,Is there a way to look for clines where the gap/distance between the edge of the cline to edge of the anti-pad is less than the width of the cline? (see attached pic)Then if found, place a...
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Change host id in license file for cadence 16.5
Hello! I want to install cadence 16.5 software to a different pc and since i have purchased only one license, i have to transfer the license server to the new machine.How can i do it? From what i...
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Is it true autorouter cannot handle 45 degree angles?
First of all, I am very very new to Cadence. I've done some board design and layout in KiCad before for a mixed-signal project. My colleagues are telling me the default autorouter in Cadence can't...
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Eagle to orCAD?
I have some Cadsoft Eagle 6x designs. Are there any tools that would hekp me convert schematics or board files?
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Create a BOM for Symbols on the bottom side of the board only ?
How does one go about generating a list for symbols located on the bottom side of the board only.It is not jumping off the page to me in reports..Thanks Scott
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How to Generate Board Information
Hi,I am going to prepare Manufacturing information of my board. I have generated Art & Drill files. However, I see extra information in some PCB layouts of other manufacturers. For exmple, they...
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Add via option not working while routing
Hi,I'm doing routing my design right now.While routing the ADD VIA option is not at all working after attempting so many times. Pls help me anyone to get a solution for this. Shreeja
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Converting .max file to .brd file
Hi everyone, i just converted my .max fles (10.5 version) to .brd files to work on the 16.5 version. After i converted my MAX file to BRD file thru orcad layout translator in 16.5 suite,...
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Footprint creation manually the refdes will get updated automatically?
Hi. I had small doubt in the footprint creation, i had tried to create the SMD Resistor footprint (SMR0805).In that, what should be the Refdes text should be entered. (i.e)., i should give text as R*...
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Manually Created foot print is get not placed in board?
Hi.. I had created the footprint with specifications with what ever in data-sheet provided. When i am try to place in manually or place all components or place with room outline, the components is not...
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Allegro Free Physical Viewer 16.6 Will Not Run
I am bringing this to the community because I have not been able to get this resolved through Cadence support so here goes...Back in early February, several product engineers running Windows 7 on Dell...
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Allegro Impedance Calculator problem
Hi,I am working on my board Stack-up to tune Single/Differential impedances of my board in Allegro PCB 16.6. I see that Dielectric Constant is 4.5 (FR-4) ! even for Conductor/Plane layers. I don't see...
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How to export FPGA pins information to a file
Hi all,I have my schematic & PCB in OrCAD Capture & Allegro PCB. I am wondering if there is a way to export FPGA pin numbers with Net Names to use it in a UCF file.I appreciate useful...
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