Hi
I am looking into chamfering the edge of PCB for Board edge connectors. I have performed fillet command earlier but new to chamfering.
Below is the description :
As seen above, the PCB edge are chamfered in thickness as well as at the corners.
Using OrCAD PCB hotfix S023.
Hello Fellow PCB Designers,
We have a 10 layer PCB design that originated in Pads and was converted over to Allegro 17.4, this is an old design but is manufacturable and works perfectly fine. When I try to generate a Gerber for the Top or Bottom layers
the Gerber comes out fine. But Most of the middle layers are Etch's and via's for power and grounds, but the Gerber's come mostly blank, there might be some details, but in the Gerber view everything is displayed correctly.
The design does have many close spacings, I have not changed anything in the constrains manager yet, turned off a lot of the DRC's, but thinking there might be something wrong with the constrains.
I find that the CSet is set to 2_18, not sure yet what this means, also there are many of these definitions, PCS 3,4,5,ect, are the same as CSet 2_18 any suggestions would be great, we are currently looking into this, have seen
that even small change in constraint manager can cause long processing and even Allegro crashing, this is a large project.
Thanks Much, Thanks, Mike Pollock.
Hi,
So I was trying to update the title block of a schematic that I have. The title block that was on there was out of date . I clicked on place --> title block and was able to find the title block that I need. I also have a .OLB file that contains that title block. Then I created a Netlist with the old BRD file as the input file (To keep it as is but modify changes) but when I do that I still do not see / cannot place the title block that I need. Under Place --> format symbols in Allegro , I do see a title block that is coming from the database (But it's the old one). I don't know what to do at this point and would appreciate any tips. I did make sure that the path to where the library is , is defined in the user preferences.
I also tried copying the title block under the library folder in capture before creating my Netlist and that did not work either.
Thank you all.
1， Some components in the installation package cannot choose to install; even if they do not choose them, they will still be installed; just less shortcut icons, the documents are still released to the installation directory.
2， "Catia Application Frame" repeat the problem?
“x:\Cadence\SPB_17.4\tools\bin“
”x:\Cadence\SPB_17.4\tools\spatial“
"Catia Application Frame" shouldn't you use the latest version?
3，Follow-up update patch cleaning the useless files and extra empty folder action !!!
The SPB17.4 installation package is currently the worst installation package I have seen for large-scale software packaging.
How do we purge/remove the duplicated vias in the same location of the PCB editor? These vias are not the one stacked and they are just blind vias running in internal layers 12-14. I find there is an additional copy of the blind via at the same location. Not sure what caused this issue.
I'd like to be able to edit a footprint for a part in my design without needing to find the footprint filepath and directly open that file in PCB Editor. I see that I can view footprints from Capture, and that doing so shows me the footprint path, but I can't find any way to launch the editor. Is there any way to go directly from a part in a Capture schematic or a placed part in a PCB Editor board design to editing that part's footprint?
Hi,
I have a monitor plugged to my laptop using a HDMI to USB adapter. When using this adapter, Allegro runs very slowly. It seems that it is not using my video card.
Is this a known issue with a workaround I can try?
Thanks,
Michael
Hello..
I'm updating part in part editor in orcad capture, and I wonder how to align pin numbers using menu or tcl/tk command.
Please, let me know. Thank you.
Hi All
I am looking for the functions which are different about OrCAD Professional and Allegro tier.
is there any resource?
regard
Hello, I was wondering how can I create variable fields in the layout.
To start, I have a template for some type of designs, and I would like that one of the texts on the silkscreen changes accordingly to an external variable, like the folder name, or a text file in the same folder.
I was thinking something similar to a page frame that changes the date automatically. How can I generate that type of fields?
As the title suggests I am unable to perform design sync between OrCAD Capture and Allegro. When I add a layout and try to sync to it I am given ERROR(ORCAP-2426): Cannot run Design Sync because of errors. See session log for error details.
Session Log
[ORPCBFLOW] : Invoking ECO dialog.
INFO(ORNET-1176): Netlisting the design
INFO(ORNET-1178): Design Name:
C:\USERS\DDOYLE\DOCUMENTS\CADENCE\BOARDS\REMOTE POWER DEVICE\CAPTURE\REMOTE_POWER_DEVICE.DSN
Netlist Directory:
c:\users\ddoyle\documents\cadence\boards\remote power device\layout\allegro
Configuration File:
C:\Cadence\SPB_17.4\tools/capture/allegro.cfg
pstswp.exe - pst - d "C:\USERS\DDOYLE\DOCUMENTS\CADENCE\BOARDS\REMOTE POWER DEVICE\CAPTURE\REMOTE_POWER_DEVICE.DSN"- n "c:\users\ddoyle\documents\cadence\boards\remote power device\layout\allegro" - c "C:\Cadence\SPB_17.4\tools/capture/allegro.cfg" - v 3 - l 31 - s "" - j "PCB Footprint" - hpath "HPathForCollision"
Spawning... pstswp.exe - pst - d "C:\USERS\DDOYLE\DOCUMENTS\CADENCE\BOARDS\REMOTE POWER DEVICE\CAPTURE\REMOTE_POWER_DEVICE.DSN"- n "c:\users\ddoyle\documents\cadence\boards\remote power device\layout\allegro" - c "C:\Cadence\SPB_17.4\tools/capture/allegro.cfg" - v 3 - l 31 - s "" - j "PCB Footprint" - hpath "HPathForCollision"
{ Using PSTWRITER 17.4.0 d001Dec-14-2021 at 09:00:49 }
INFO(ORCAP-36080): Scanning netlist files ...
Loading... c:\users\ddoyle\documents\cadence\boards\remote power device\layout\allegro\pstchip.dat
Loading... c:\users\ddoyle\documents\cadence\boards\remote power device\layout\allegro\pstchip.dat
Loading... c:\users\ddoyle\documents\cadence\boards\remote power device\layout\allegro\pstxprt.dat
Loading... c:\users\ddoyle\documents\cadence\boards\remote power device\layout\allegro\pstxnet.dat
packaging the design view...
Exiting... pstswp.exe - pst - d "C:\USERS\DDOYLE\DOCUMENTS\CADENCE\BOARDS\REMOTE POWER DEVICE\CAPTURE\REMOTE_POWER_DEVICE.DSN"- n "c:\users\ddoyle\documents\cadence\boards\remote power device\layout\allegro" - c "C:\Cadence\SPB_17.4\tools/capture/allegro.cfg" - v 3 - l 31 - s "" - j "PCB Footprint" - hpath "HPathForCollision"
INFO(ORNET-1179): *** Done ***
This issue started to occur after I changed parts that exist on previously created PCBs. I changed the following leading up to this:
1. Added height in Allegro to many of my components using the Setup->Area->Package Height tool.
2. Changed the reference designator category in OrCAD Capture to TP for several components on board.
Any advice here would be most welcome. Thanks!
I'm not able to export a CIS Standard BOM to a Microsoft 365 Excel (business subscription, version 2111).
Selecting the "Export BOM report to Excel" option opens a new Excel window, but OrCAD (17.4-2019 S023) won't fill it with any data...
I tried it on a different PC with Microsoft Office Professional Plus 2019 Excel (strangely the version number is the same: 2111) and with OrCAD 17.4-2019 S016 and it worked flawlessly.
Does anybody experiencing the same issue?
Does the Excel variant, the OrCAD version or the PC itself causing this?
Thanks for any help!
The default position of the pin number is incorrect.
Allegro part of DPI does not support scaling above 150%
I have managed to convert our old schematic and PCD file to from Layout 16.2 to 17.4
I have exported the footprints and moved them to the correct lib directory.
I get no DRC errors and I can build a new netlist file. The problem is I can't get the PCB editor to update using the new netlist and get the following error:
I cannot figure out how to fix the Name is too long error.
(---------------------------------------------------------------------)( )( Allegro Netrev Import Logic )( )( Drawing : 70055R2.brd )( Software Version : 17.4S023 )( Date/Time : Tue Dec 14 18:54:25 2021 )( )(---------------------------------------------------------------------)------ Directives ------------Ripup etch: YesRipup delete first segment: NoRipup retain bondwire: NoRipup symbols: IfSameMissing symbol has error: NoDRC update: YesSchematic directory: 'C:/AFS/70055 PCB Test 2'Design Directory: 'C:/AFS/70055 PCB Test 2'Old design name: 'C:/AFS/70055 PCB Test 2/70055R2.brd'New design name: 'C:/AFS/70055 PCB Test 2/70055R2.brd'CmdLine: netrev -$ -i C:/AFS/70055 PCB Test 2 -x -u -t -y 2 -h -z -q netrev_constraint_report.xml C:/AFS/70055 PCB Test 2/#Taaaaae57776.tmp------ Preparing to read pst files ------Starting to read C:/AFS/70055 PCB Test 2/pstchip.dat Finished reading C:/AFS/70055 PCB Test 2/pstchip.dat (00:00:00.02)Starting to read C:/AFS/70055 PCB Test 2/pstxprt.dat Finished reading C:/AFS/70055 PCB Test 2/pstxprt.dat (00:00:00.00)Starting to read C:/AFS/70055 PCB Test 2/pstxnet.dat Finished reading C:/AFS/70055 PCB Test 2/pstxnet.dat (00:00:00.00)------ Oversights/Warnings/Errors ------#1 ERROR(SPMHNI-176): Device library error detected.ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_9_SWITCH_OTTO_ALT_SW DPDT': 'Name is too long.'.ERROR(SPMHNI-170): Device 'SW DPDT_9_SWITCH_OTTO_ALT_SW DP' has library errors. Unable to transfer to Allegro.#2 ERROR(SPMHNI-176): Device library error detected.ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_10_SWITCH_OTTO_LIGHTS_SW DPDT': 'Name is too long.'.ERROR(SPMHNI-170): Device 'SW DPDT_10_SWITCH_OTTO_LIGHTS_S' has library errors. Unable to transfer to Allegro.#3 ERROR(SPMHNI-176): Device library error detected.ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_7_SWITCH_OTTO_ALT_SW DPDT': 'Name is too long.'.ERROR(SPMHNI-170): Device 'SW DPDT_7_SWITCH_OTTO_ALT_SW DP' has library errors. Unable to transfer to Allegro.#4 ERROR(SPMHNI-176): Device library error detected.ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_3_SWITCH_OTTO_MASTER_SW DPDT': 'Name is too long.'.ERROR(SPMHNI-170): Device 'SW DPDT_3_SWITCH_OTTO_MASTER_SW' has library errors. Unable to transfer to Allegro.#5 ERROR(SPMHNI-176): Device library error detected.ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_6_SWITCH_OTTO_LIGHTS_SW DPDT': 'Name is too long.'.ERROR(SPMHNI-170): Device 'SW DPDT_6_SWITCH_OTTO_LIGHTS_SW' has library errors. Unable to transfer to Allegro.#6 ERROR(SPMHNI-176): Device library error detected.ERROR(SPMHNI-189): Problems with the name of device 'SW DPDT_3_SWITCH_OTTO_MASTER_DPDT': 'Name is too long.'.ERROR(SPMHNI-170): Device 'SW DPDT_3_SWITCH_OTTO_MASTER_DP' has library errors. Unable to transfer to Allegro.#7 ERROR(SPMHNI-176): Device library error detected.ERROR(SPMHNI-189): Problems with the name of device 'CONNECTOR DB15_DSUBVPTM15_CONNECTOR DB15': 'Name is too long.'.ERROR(SPMHNI-170): Device 'CONNECTOR DB15_DSUBVPTM15_CONNE' has library errors. Unable to transfer to Allegro.#8 ERROR(SPMHNI-176): Device library error detected.ERROR(SPMHNI-189): Problems with the name of device 'CONNECTOR DB9_DSUBVPTM9_CONNECTOR DB9': 'Name is too long.'.ERROR(SPMHNI-170): Device 'CONNECTOR DB9_DSUBVPTM9_CONNECT' has library errors. Unable to transfer to Allegro.#9 ERROR(SPMHNI-175): Netrev error detected.ERROR(SPMHDB-195): Error processing 'M6': Text line is outside of the extents..------ Library Paths ------MODULEPATH = . C:/Cadence/SPB_17.4/share/local/pcb/modules PSMPATH = . symbols .. ../symbols C:/Cadence/SPB_17.4/share/local/pcb/symbols C:/Cadence/SPB_17.4/share/pcb/pcb_lib/symbols C:/Cadence/SPB_17.4/share/pcb/allegrolib/symbols C:/Cadence/SPB_17.4/share/pcb/pcb_lib/symbols PADPATH = . symbols .. ../symbols C:/Cadence/SPB_17.4/share/local/pcb/padstacks C:/Cadence/SPB_17.4/share/pcb/pcb_lib/symbols C:/Cadence/SPB_17.4/share/pcb/allegrolib/symbols C:/Cadence/SPB_17.4/share/pcb/pcb_lib/symbols ------ Summary Statistics ------#10 Run stopped because errors were detectednetrev run on Dec 14 18:54:25 2021 DESIGN NAME : '70055R2' PACKAGING ON Nov 2 2021 14:32:04 COMPILE 'logic' CHECK_PIN_NAMES OFF CROSS_REFERENCE OFF FEEDBACK OFF INCREMENTAL OFF INTERFACE_TYPE PHYSICAL MAX_ERRORS 500 MERGE_MINIMUM 5 NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|' NET_NAME_LENGTH 24 OVERSIGHTS ON REPLACE_CHECK OFF SINGLE_NODE_NETS ON SPLIT_MINIMUM 0 SUPPRESS 20 WARNINGS ON 10 errors detected No oversight detected No warning detectedcpu time 0:00:27elapsed time 0:00:00
Hi All
I followed tutorial video below for using Design link
https://www.youtube.com/watch?v=f9JmFF8lqA0
and I followed the video with embedded board design file which should be same one on video
I did every set. but at 2:55 of video, Steve have the tabs of both design names on top of Constraint Manager in video
but my one didn't exist them
which one would be different?
there was some comment on command windows but I think they would not be problem here
regard
Hello. I am using Cadence 17.4 tools. When I open a package symbol (.dra) or board file (.brd) in Allegro that was created in an older version of the tool I get a message like this one (as expected):
"The design created using release 17.2 will be updated for compatibility with the current software..."
If I create a symbol or board file from scratch in the 17.4 tool then open it later, I get the same message. (always referring to version 17.2 which is the previous version I was using here).
So far this has not caused me any problems, but I would like to understand why it is doing this in case I have something setup incorrectly.
I only have version 17.4 installed. I am not exporting to a downrev version when I save (i.e. not using File->Export->Downrev design…) and in User Preferences->Drawing I don’t have anything selected for database_compatibility_mode. What else might I check?
FYI here is the tool version information that I see after selecting Help->About Symbol:
OrCAD PCB Designer Standard 17.4-2019 S012 [10/26/2020] Windows SPB 64-bit Edition
Thanks -Jason
I have a small board that is not readable even though the document is 11' x 17'. Is there a way I could expand/magnify the board along with the components on them to make them legible?
I have created a new film and is displaying the bottom and top side of the board but the board is too small and the components are not legible. Perhaps there is a way to upscale it or expand it?
Please note I have other stuff in the document that I am not showing , notes and other things, and I am trying to make just the boards look bigger in some way.
I do have a PDF image of the same file where the board appears to be MUCH bigger and is fully legible and I am trying to match that.
Thank you all.
When using Shape > Create Bounding Shape on an arc, the outer side works well, but on the inner side it just draws a straight line from the begging to the end of the curve. Is anyone aware of a fix for this?
I'm attaching a picture as an example, it works great on lines.
Hello All,
I'm a novice to this forum and probably this subject has been already discussed here.
My company has purchased OrCAD Capture 17.4 tools that have a new GUI if compared to my earlier used OrCAD Capture 9.2. I have been using Capture 9.2 for ~18 years and its GUI is really convenient. The GUI of 17.4 looks to be a modern one with new icons and really has improved features and new capabilities.
However, my main complain about GUI 17.4 is that the schematic windows cannot be cascaded. Although they can be set floating, this is even more annoying because all toolbars remain in the Capture window and when you select a tool, the Capture window pops over already open schematic window and you need a lot of useless extra clicks to return back to the currently edited schematic page. I always used cascading of schematic windows before because my complex designs includes many pages, not speaking about the library windows that are typically open simulatneously. My view is that the lack of CASCADING in Capture GUI 17.4 is critical and unacceptable for complex projects, and I would very highly appreciate if the Cadence guys will return back the CASCADING capability for schematic pages. In case this will be done, this will make the GUI really great and comfortable to use.
Does anybody have opinion on this issue?
Many thanks,
Pavel
hello,
We have a number of workstations with version 17.2 that work on a floating license server
We want to know if it can be upgraded to version 17.4
If so, should the floating license server be upgraded as well?
In addition, how can you know where the license was purchased from?
Thanks!
Hello,
A mybe silly question came to my mind: When routing sense lines, is it better to hav them as close as possible to DUT or afer the decoupling capacitors ?
Force in red, sense in purple.
Best way is 1 or 2 ?
Thanks in advance and Merry Christmas to everybody !
hello:
i use the command "net logic" to change/assign the net name of the pins but the command can be used for only one pin at a time.
is there a way to change/assign the same net name on 100 pins all at once?
i have a daisy chain design so i need to assign one net name for 100s of pins.
I have a design which says there are 6 unconnected nets. But 'Display All Nets, shows only 4 unconnected. When I try to look at the non-connection, is appears connected and nothing shows??
What is happening?
Hi,
I found that under the Dark Theme of PCB Environment Editor 17.4,
the window background is not all dark, resulting in unclear text display。
As shown in the figure below：
