Hi,
I am new to Allegro PCB Designer 16.6
How to replace existing foot print for Resistor 0805 to 0402 package
Thanks
Prem
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How to replace foot print for Resistor 0805 to 0402 package
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Cannot load symbol '0402'
I have edited and kept the file name 0402.dra in my custom library folder.
path is PSM
If i place the component , it gives the following error
Cannot load symbol '0402'
Please help to find the error.
Thanks
Prem
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Toolbar settings in Orcad Capture CIS V17.2
Is it possible to save the toolbar settings in Orcad Capture CIS 17.2?
Every time I start Orcad it comes up with the same settings.
Ralf
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routing design
tthere are two questions .
1 QFP solder atc foot problems... Keep isolated? Or the earth? what is the effect when designing and processing?
2 Solder wire is generally not recommended from the four corners, especially the small seal fabrication, why? What are the effects?
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impedance matching
Hi,
In my circuit, a chip antenna(ANT016008LCS2442MA2)is used in the circuit for Bluetooth low energy. Balun(HHM1711D1)is used for impedance matching and to achieve compatibility between feedline and antenna.It's recommended to connect BLE pins & balun with 100 ohm differential lines and balun & chip antenna with 50ohm differential pair. How can i match a trace for a particular impedance. I think the impedance depends most importantly on the trace width and also the thickness of the dielectric right? So I think i need to consult with the pcb fab house. Am i right? What are the parameters that i should ask them to get my PCB done as per the recommendation?
Any help would be appreciated
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Custom PAD design/PAD designer
Hi
I want to create a individual PAD/pads for a bluetooth module(size 10x10), these pads are placed at the edge of the PCB such that it will be used to solder onto the PCB(Base Board)
How to create such pads(custom)?. Is there any standards to be followed? Kindly help and advice.
Ex: silicon labs BLE112 ( Pads as seen on the edge of the module PCB).
Many Thanks
LN
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Footprint of Si1143 Gesture Control
Hi All,
I was making the footprint of Si114x Sensor. As the dimensions are given in the datasheet
I chose the pad dimensions
Width=12 mils
Height = 16 mils
For making footprint
The package type is 10-QFN, So I chose PLLC/QFP package
Vertical pin count=4
Horizontal Pin count=1
Lead Pitch=20 mils
e1=95
e2 =95
D=79
E=79
then it is showing 6 DRC error.
I don't know, what mistake that i am doing.
please see the datasheet
https://www.silabs.com/Support%20Documents/TechnicalDocs/Si114x.pdf
Can somebody suggest me how to resolve this problem?
Thanks in advance.
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Default grid in symbol editor?
The symbol editor defaults to 0.635 and 2.54 grids. Fair enough. But I don't want that so I have to go and change them every time I make a new footprint.
Is there any way to change the default grid? I tried googling it but curiously nobody even asks about it..
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Pspice multiple cursors?
Hi there!
Could ORCAD Pspice display multiple cursors, like three cursors or more? I can just enable two cursors to the most. Thanks!
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Zoom in gives blue color screen
Hi
I am using Allegro PCB Designer Ver 16.6, When ever i zoom by mouse wheel , the blue color screen appears .
How to solve this issue.
Thanks
Prev
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Area arround pin- PCB designer
Hello Everyone,
I have problem with pins that I used as mounting holes.
Some addidional copper void area is arround and I do not want it.
That component is not only mechanical pin, because I have added
it to schematic and grounded. 
Where I can find option to make that void area disabled?
I am using PCB Designer Professional 16.6.
Best regards,
Chris
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.pcb File conversion
I have a design that was provided by a contractor that we wish to convert to Altium 6.1. The .dsn file was successfully imported but the .pcb file will not import with any of the tools provided in Altium.
The header in the .DSN file has "Orcad 10.3" in it, but the .pcb has no header info.
A .pcb file could be a LOT of things and since the schematic header says 10.3 I assume the layout is the same?
Tried opening it in CIS 10.3 but won't work.
Can anyone give me a clue what I can do to either display this database or import it?
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The Economics of Reducing Cycle Time in PCB Fabrication
a good article and an active opinion about the process of pcb design.
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OK unassigned shape in Allegro
How do I select "OK unassigned shape" in Allegro 16.6? Where is it hidden? I have a shape connected to a mechanical pin with no net name. I don't want to see the error.
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6 layer PCB
Hi All,
I am making the PCB of Si1143 Gesture Sensor . Now I am ConfUse for the layer that I am going to add in Layout Cross section.
1. Top
2. Bottom
3. Vcc
4. Gnd
So how can I include two more layer?
Can somebody suggest me ?
Thanks in advance.
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Non plated holes error is not showing in cadence PCB design
Hi all,
In my design two non plated holes are there. two different traces are passing through the non plated holes in inner layers, but not showing error.
please find attached snap short,
any one help me.
Thanks,
Balaji
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Silkscreen Automatic Clearance adjustment
Is there any way of setting a DRC or the Auto-silk to ensure clearance from the solder mask on pads?
I know there is the auto-align, but this can put idents is such obscure locations that it is impossible to know which device the ident relates to. I work on very high density PWA's.
If there is some way of using the ident layer and get the auto-silk to remove all violating sections of the ident, I can then adjust the position of the ident so that it becomes visible (I know that some idents could look wrong if they are not placed correctly, like a R29 looking like R25 if there is a pad near the ident, but I can manually check for this after the auto-silk is generated and move the ident to have a better view and then regenerate the auto-silk).
But when the auto-silk generates an ident that is 5 components away from the item it is supposed to identify, this is unacceptable. I know I can set the limit that the auto-silk can move the ident, but this has the habit of placing idents over other idents or even over components.
The best solution would be, if the online DRC error checked the ident in the first place so that it can be placed in a location that does not violate pad or copper clearances.
[Please visit the site to access the poll]
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Room spacing constraint
Is it possible to define a spacing in the constraint manager between components that have associated different room parameters to them?
So for example two resistors which belong to room 1 and room 2 and I want to make sure that the minimal spacing is 2mm.
Regards,
David
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Designers and Design Engineers: Two Sides of the Same Coin
Andy and Sue Critcher have been the lead designers at Total Board Solutions Limited, a UK-based design bureau, since its founding in 1998. I asked Andy to share his opinion about the friction between some PCB designers and their engineers, and what can be done to improve communications between these groups.
Andy Shaughnessy: Andy, tell us a little bit about your company and how you operate.
Andy Critcher: Total Board Solutions Limited (TBS) is a design services bureau based in the UK. We fit into our customer’s design process, providing whatever is not a core competency. This means that for some customers we perform just the layout portion of their design while for others we enter the schematic, libraries, create the layout and even get the boards fabricated and assembled—no two customers are exactly the same. When working with startups we provide the link between the concept, or idea, and product realization; providing knowledge of design process, fabricators capabilities and our experience when discussing the inevitable tradeoffs between the requirement and what is possible.
Shaughnessy: A recent survey of our PCB designer readers found that there’s often friction between PCB designers and engineers. Some designers say, only half-jokingly, that their EEs are their biggest challenge. Why do you think there’s such disconnect?
Critcher: Looking solely from the PCB side, I think that the disconnect mainly arises from the lack of understanding of what a PCB designer actually does, it is perceived as a simple task of dot joining and that anyone can do it. I know that this is a bit of a cliché but it does seem to hold true. As an example, in a number of the companies that I have worked with, PCB progress meetings are held and the PCB designer is never asked to attend; their input can be easily be determined by the engineering team/project manager.
This perception is backed up by the lack of formal qualification for PCB designers—for my generation, we generally started off as mechanical draughtsman in the traditional drawing office and then moved to the PCB section.
This perception means that the status of the PCB designer is quite low, so when they advise the engineer that something is not possible this can be met with a certain amount of derision. The engineer possibly thinks that the PCB designer is just being obstructive, while conversely, the PCB designer thinks that the engineer is very dismissive of his knowledge, capabilities, opinion, etc.
Let’s look at the issue from the engineer’s perspective. By providing design consultancy, we are fortunate enough to be a lot more involved in the engineer’s world, including some of the problems that they have to deal with as part of the overall product development. One engineer explained that the design part was relatively straightforward, but the need to meet cost, functionality, component sourcing, obsolescence, test plans, as well as reading through 150+ pages of documentation on a device’s timing “makes life interesting.” As PCB designers, we tend to have a lot of questions, especially about the newer technology, so we can bombard the engineer with a number of questions concerning unfamiliar topics expecting immediate answers, and normally at this point the pressure to get it finished is already building.
from
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IDF out problems to Solidworks 2016
I am having strange problems when I output an IDF file out of Allergro PCB Designer and send to our mechanical group using Solidworks. Sometimes the component height goes through, in the IDF file, and sometimes it doesn't. I assume this value is derived in the IDF translator from the PLACE_BOUND_TOP > PACKAGE_HEIGHT_MAX attribute??? Sometimes mounting holes show up in solidworks and sometimes they do not. I add a PLACE_BOUND_TOP > PACKAGE_HEIGHT_MAX shape, with a low height value. I can't find any literature on IDF in Cadence to indicate what properties the IDF export tool uses when it does the translation out of Allegro into IDF? Any ideas?
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